Troubleshoot UDC port configurations by clearing statistics and checking port attributes, port state, VLAN lists, and port counters.
Table 1.
Feature History
| Feature Name |
Release |
Description |
| Troubleshooting User Data Channel (UDC) Port Configurations |
Cisco IOS XR Release 7.8.1 |
The hw-module and show hw-module commands have been enhanced with additional keywords to improve the troubleshooting of issues on UDC ports. Apart from viewing the UDC port state, VLAN list, and port statistics, you can clear UDC port configurations and enable or disable configurations on each UDC port. |
From Release 7.8.1, the hw-module eth-switch and show hw-module eth-switch commands provide options to troubleshoot UDC ports and view the current configuration.
Note
The hw-module eth-switch clear-stats command clears all the counters on the selected port and turns off the Clear-On-Read attribute. You can re-enable Clear-On-Read with the enable-clear-on-read attribute.
Procedure
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1. |
Clear the statistics configured for UDC port 1.
Example:
RP/0/RP0/CPU0:ios#configure
RP/0/RP0/CPU0:ios(config)#hw-module eth-switch clear-stats port Rj45Udc1
RP/0/RP0/CPU0:ios(config)#commit
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2. |
Clear the statistics configured for all the ports.
Example:
RP/0/RP0/CPU0:ios#configure
RP/0/RP0/CPU0:ios(config)#hw-module eth-switch clear-stats all
RP/0/RP0/CPU0:ios(config)#commit
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3. |
Display the configured attributes of the UDC ports.
Example:
RP/0/RP0/CPU0:ios#show hw-module eth-switch ports-attrs
This output shows the attributes of all the configured ports.
Thu Nov 10 13:24:16.932 CET
Ports Attributes:
Port SfpUdc3 # 0 (enable) Link UP Full-Duplex 9604 [1 Gbps] 6(1000BASE_X) Clear-On-Read
Port SfpUdc2 # 4 (enable) Link UP Full-Duplex 9604 [1 Gbps] 6(1000BASE_X) Clear-On-Read
Port SfpUdc1 # 8 (enable) Link UP Full-Duplex 9604 [1 Gbps] 6(1000BASE_X) Clear-On-Read
Port Rj45Udc1 # 12 (enable) Link DOWN Half-Duplex 9600 [1 Gbps] 3(SGMII) Clear-On-Read
Port Rj45Udc2 # 16 (enable) Link DOWN Half-Duplex 9600 [1 Gbps] 3(SGMII) Clear-On-Read
Port Rj45Udc3 # 20 (enable) Link DOWN Half-Duplex 9600 [1 Gbps] 3(SGMII) Clear-On-Read
Port CpuMgmt # 24 (enable) Link UP Full-Duplex 1522 [1 Gbps] 6(1000BASE_X)
Port # 25 (enable) Link UP Full-Duplex 1522 [1 Gbps] 6(1000BASE_X)
Port Rj45Mgmt # 26 (enable) Link UP Full-Duplex 1522 [1 Gbps] 3(SGMII)
Port SfpMgmt # 27 (enable) Link DOWN Half-Duplex 1522 [1 Gbps] 3(SGMII)
The command output displays the link state, duplex mode, maximum transmission unit, speed, interface type, and Clear-On-Read status for each configured port.
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4. |
Display the counters that are related to the CpuMgmt port.
Example:
RP/0/RP0/CPU0:ios#show hw-module eth-switch stats port CpuMgmt
This output displays the counter values for the CpuMgmt port.
Mon May 16 09:10:24.491 UTC
****************** START ******************
PORT MAC COUNTERS - Test cmd [1] [Port:0x18]
goodPktsSent 0
goodPktsRcv 0
ucPktsSent 17
ucPktsRcv 2
mcPktsSent 1489
mcPktsRcv 0
brdcPktsSent 349
brdcPktsRcv 1
goodOctetsSent 200863
goodOctetsRcv 474
pkts64Octets 614
pkts65to127Octets 872
pkts128to255Octets 86
pkts256to511Octets 286
pkts512to1023Octets 0
pkts1024tomaxOoctets 0
pkts1024to1518Octets 0
The command output displays MAC counter values, including packets, octets, and packet-size counters for the CpuMgmt port.
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5. |
Enable MAC counters Clear-On-Read for the Rj45Udc1 port.
Enabling or disabling MAC counters Clear-On-Read affects the corresponding port pairs: SfpUdc3 #0 and SfpUdc2 #4, and Rj45Udc1 #12 and Rj45Udc2 #16. Configuring this attribute on Rj45Udc1 #12 also affects Rj45Udc2 #16 and the other way around.
Example:
RP/0/RP0/CPU0:ios#configure
RP/0/RP0/CPU0:ios(config)#hw-module eth-switch port Rj45Udc1 enable-clear-on-read
RP/0/RP0/CPU0:ios(config)#commit
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6. |
Verify the hardware module Ethernet switch port attributes.
Example:
RP/0/RP0/CPU0:ios#show hw-module eth-switch ports-attrs
Ports Attributes:
Port SfpUdc3 # 0 (enable) Link UP Full-Duplex 9604 [1 Gbps] 6(1000BASE_X)
Port SfpUdc2 # 4 (enable) Link UP Full-Duplex 9604 [1 Gbps] 6(1000BASE_X)
Port SfpUdc1 # 8 (enable) Link UP Full-Duplex 9604 [1 Gbps] 6(1000BASE_X)
Port Rj45Udc1 # 12 (enable) Link UP Half-Duplex 9600 [1 Gbps] 3(SGMII) Clear-On-Read
Port Rj45Udc2 # 16 (enable) Link UP Half-Duplex 9600 [1 Gbps] 3(SGMII) Clear-On-Read
Port Rj45Udc3 # 20 (enable) Link UP Full-Duplex 9600 [1 Gbps] 3(SGMII)
Port CpuMgmt # 24 (enable) Link UP Full-Duplex 1522 [1 Gbps] 6(1000BASE_X)
Port # 25 (enable) Link UP Full-Duplex 1522 [1 Gbps] 6(1000BASE_X)
Port Rj45Mgmt # 26 (enable) Link UP Full-Duplex 1522 [100 Mbps] 3(SGMII)
Port SfpMgmt # 27 (enable) Link DOWN Half-Duplex 1522 [1 Gbps] 3(SGMII)
The command output shows whether Clear-On-Read is enabled for the expected UDC ports.
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The UDC port statistics and Clear-On-Read behavior are updated and verified from the hardware module Ethernet switch command output.