Memory
The following table lists the memory BIOS settings that you can configure through a BIOS policy or the default BIOS settings:
Name |
Description |
Supported Attributes |
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Versions |
Platforms |
Values |
Dependencies |
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Enhanced Memory Test | Enables enhanced memory tests during the system boot and increases the boot time based on the memory. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.2(1), 5.0(1), 5.0(2) |
C220 M5, C240 M5, B200 M6, C220 M6,C240 M6, C225 M6, C245 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Enabled, Auto
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It is recommended to leave this setting in the default state of Auto. |
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BME DMA Mitigation |
Allows you to disable the PCI BME bit to mitigate the threat from an unauthorized external DMA |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.2(1) |
C220 M5, C240 M5, B200 M6, C240 M6, C225 M6, C245 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Enabled, Disabled
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Burst and Postponed Refresh |
Allows the memory controller to defer the refresh cycles when the memory is active and accomplishes the refresh within a specified window. The deferred refresh cycles may run in a burst of several refresh cycles. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.2(1) |
C225 M6 and C245 M6 |
Enabled, Disabled
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CPU SMEE |
Whether the processor uses the Secure Memory Encryption Enable (SMEE) function, which provides memory encryption support. |
4.0(2), 4.0(4), 4.1(1), 4.2(1) |
C125 M6, C225 M6, C245 M6 |
Disabled, Enabled, Auto
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IOMMU |
Input Output Memory Management Unit(IOMMU) allows AMD processors to map virtual addresses to physical addresses. |
4.0(2), 4.0(4), 4.1(1), 4.2(1) |
C125 M6, C225 M6, C245 M6 |
Disabled, Enabled, Auto
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Bank Group Swap |
Determines how physical addresses are assigned to applications. |
4.0 (1), 4.0(4), 4.1(1)4.2(10 |
C125 M5, C225 M6, C245 M6 |
Disabled, Enabled, Auto
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Chipset Interleave |
Whether memory blocks across the DRAM chip selects for node 0 are interleaved. |
4.2(1) |
C225 M6, C245 M6 |
Disabled, Enabled, Auto
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SNP Memory Coverage |
This option selects the operating mode of the Secured Nested Paging (SNP) Memory and the reverse Map Table (RMP). The RMP is used to ensure a one-to-one mapping between system physical addresses and guest physical addresses. |
4.2(1) |
C225 M6, C245 M6 |
Disabled, Enabled, Auto
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SNP Memory Size to Cover in MiB |
Allows you to configure SNP memory size. |
4.2(1) | C225 M6, C245 M6 |
Disabled, Enabled, Auto
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NUMA Nodes per Socket |
Enables or disables MMIO above 4GB or not. |
4.2(1) |
C225 M6, C245 M6 |
Auto, NPS0, NPS1, NPS2, NPS4
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AMD Memory Interleaving |
Determines the memory blocks to be interleaved. It also determines the starting address of the interleave (bit 8,9,10 or 11). |
4.0(2), 4.0(4), 4.1(1) |
C125 M5 |
Auto, Channel, Die, none, Socket |
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AMD Memory Interleaving Size |
Determines the size of the memory blocks to be interleaved. It also determines the starting address of the interleave (bit 8,9,10 or 11). |
4.0(2), 4.0(4), 4.1(1) |
C125 M5 |
1 KB, 2 KB, 256 Bytes, 512 Bytes, Auto |
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SEV-SNP Support |
Allows you to enable Secure Nested Paging feature. |
4.2(1) |
C225 M6, C245 M6 |
Disabled, Enabled
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CR QoS |
Prevents DRAM and overall system BW drop in the presence of concurrent DCPMM BW saturating threads, with minimal impact to homogenous DDRT-only usages, Good for multi-tenant use cases, VMs, etc. Targeted for App Direct, but also improves memory mode. Targets the “worst-case” degradations. |
4.1(2), 4.2(1), 5.0(1), 5.0(2) |
C220 M5, C240 M5, C220 M6, C240 M6 servers, B200 M6, and X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Recipe 1, Recipe 2, Recipe 3, Mode 0, Mode 1, Mode 2
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CR FastGo Config |
CR FastGo Config improves DDRT non-temporal write bandwidth when FastGO is disabled. When FastGO is enabled, it gives faster flow of NT writes into the uncore, When FastGO is disabled, it lessens NT writes queueing up in the CPU uncore, thereby improving sequentially at DCPMM, resulting in improved bandwidth. |
4.1(2), 4.2(1), 5.0(1), 5.0(2) |
C220 M5, C240 M5, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Auto, Option 1—5, Enable Optimization, Disable Optimization |
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DCPMM Firmware Downgrade | To configure DCPMM Firmware Downgrade. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.2(1) |
B480 M5, C220 M5, C240 M5, C480 M5, C220 M6, C240 M6, C220 M7, C240 M7, X210c M7, X410c M7 servers |
Disabled, Enabled
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DRAM Refresh Rate |
To configure the refresh interval rate for internal memory. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.2(1) |
C125 M5 |
Auto, 1x, 2x, 3x, 4x |
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DRAM SW Thermal Throttling |
To configure DRAM SW thermal throttling. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1) |
C125 M5 |
Disabled, Enabled
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eADR Support |
Extended asynchronous DRAM refresh (eADR) ensures that CPU caches lines with data are flushed at the right time and in the desired order and are also included in the power fail protected domain. |
4.2(1), 5.0(1), 5.0(2) |
B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Enabled, Auto
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Low Voltage DDR Mode |
Whether the system prioritizes low voltage or high frequency memory operations. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1) |
All M5 servers |
Auto, Power Saving Mode, Performance Mode
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Memory Bandwidth Boost |
Allows to boost the memory bandwidth. |
4.2(1), 5.0(1), 5.0(2) |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Enabled
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Memory Refresh Rate |
Controls the refresh rate of the memory controller and might affect the memory performance and power depending on memory configuration and workload. |
4.0(2), 4.0(4), 4.1(1), 4.2(1), 5.0(1), 5.0(2) |
C220 M5, C240 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
1x Refresh, 2x Refresh
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Memory Size Limit in GiB |
Limits the capacity in Partial Memory Mirror Mode up to 50 percent of the total memory capacity. The memory size can range from 0 GB to 65535 GB in increments of 1 GB. |
4.0(2), 4.0(4), 4.1(1), 4.2(1) |
C220 M5, C240 M5, B200 M6, C240 M6, C225 M6, C245 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
0 - 65535 with a step size of 1 |
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Memory Thermal Throttling Mode |
Provides a protective mechanism to ensure the memory temperature is within the limits. When the temperature exceeds the maximum threshold value, the memory accessrate isreduced and Baseboard Management Controller (BMC) adjusts the fan to cool down the memory to avoid DIMM damage due to overheat |
4.0 (1), 4.0(2), 4.0(4), 4.1(1) |
All M5 servers and , C220 M7, C240 M7 , X210c M7, X410c M7 servers |
CLTT with PECI, Disabled
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This token is not supported on C125 M5 servers. |
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Mirroring Mode |
Memory mirroring enhances system reliability by keeping two identical data images in memory. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1) |
All M5 servers |
Inter-socket, Intra-socket
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NUMA Optimized |
Whether the BIOS supports NUMA. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1) |
C220 M5, C240 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Enabled, Disabled
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NVM Performance Setting |
enables efficient major mode arbitration between DDR and DDRT transactions on the DDR channel to optimize channel BW and DRAM latency. |
4.0(2), 4.0(4), 4.1(1) |
C220 M5, C240 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
BW Optimized, Latency Optimized, Balanced Profile
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Operation Mode |
This option allows you to configure Operation Mode. |
4.2(1), 4.2(2) |
C225 M5, C245 M5 |
Test-Only, Test and Repair |
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Panic and High Watermark |
Controls the delayed refresh capability of the memory controller. |
4.2(1) |
B200 M6, C220 M6, C240 M6, C220 M7, C240 M7, X210c M7, X410c M7 |
High, Low
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It is recommended to leave this setting in the default state (Low) which will help to reduce susceptibility to Rowhammer-style attacks. |
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Partial Cache Line Sparing |
Partial cache line sparing (PCLS) is an error-prevention mechanism in memory controllers. PCLS statically encodes the locations of the faulty nibbles of bits into a sparing directory along with the corresponding data content for replacement during memory accesses. |
4.2(1), 5.0(1), 5.0(2) |
B200 M6, C240 M6, C220 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Enabled
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Partial Memory Mirror Mode |
enables you to partially mirror by GB or by a percentage of the memory capacity. Depending on the option selected here, you can define either a partial mirror percentage or a partial mirror capacity in GB in available fields. You can partially mirror up to 50 percent of the memory capacity. |
4.1(1), |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Percentage, Value in GB
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Partial Mirror Percentage |
Limits the amount of available memory to be mirrored as a percentage of the total memory. This can range from 0.000.01 % to 50.00 % in increments of 0.01 %. |
4.1(1) |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
0.00 - 50.00 with a step size of 0.01 |
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Partial Mirrorn Size in GB, where n ranges from 1 to 4. |
Limits the amount of memory in Partial Mirrorn in GB. This can range from 0 GB to 65535 GB in increments of 1 GB. |
4.1(1) |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, C125 M5, C220 M7, C240 M7, X210c M7, X410c M7 |
0 - 65535 with a step size of 1 |
When n=2:
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PCIe RAS Support | Whether the PCIe RAS port is enabled or disabled. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.1(3) |
All M5 servers and , C220 M7, C240 M7 , X210c M7, X410c M7 servers |
Disabled, Enabled, Auto
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Post Package Repair |
Post Package Repair (PPR) provides the ability to repair faulty memory cells by replacing them with spare cells. |
4.2(1) |
B200 M6, C240 M6, C220 M6, C225 M6, C245 M6, X210c M6 |
Disabled, Hard PPR
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Memory RAS Configuration |
How the memory reliability, availability, and serviceability (RAS) is configured for the server. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.1(3), 4.2(1), 5.0(1), 5.0(2) |
C220 M5, C240 M5, B200 M6, C240 M6, C220 M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Maximum Performance, Mirroring, Lockstep, Mirror Mode 1LM, Partial Mirror Mode 1LM, Sparing, ADDDC Sparing
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PPR Type |
Post Package Repair (PPR) provides the ability to repair faulty memory cells by replacing them with spare cells. |
4.1(1), 4.2(1) |
C220 M5, C240 M5, B200 M5, B200 M6, C240 M6, C220 M6, C225 M6, C245 M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Hard PPR
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Secured Encrypted Virtualization |
Enables running encrypted virtual machines(VMs) in which the code and data of the VM are isolated. |
4.2(1) |
C125 M5, C225 M6, C245 M6 |
253 ASIDs, 509 ASIDs, Auto
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SMEE |
Whether the processor uses the Secure Memory Encryption Enable (SMEE) function, which provides memory encryption support. |
4.0(4), 4.1(1), 4.1(3), 4.2(1) |
C125 M5, C225 M6, C245 M6 |
Disabled, Enabled
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Snoopy Mode for 2LM |
Enables snoop-mode for DCPMM accesses while maintaining directory on all DRAM accesses. Snoops maintain cache coherence between sockets. Directory reducessnoops by keeping the remote node information locally (in memory). Directory lookups and updates add memory traffic Directory is a good tradeoff for DRAM, but not necessarily for DCPMM. For non-NUMA workload, when the feature is enabled, directory updates to DCPMM are eliminated, thereby helping DDRT bandwidth bound workloads. Directory is disabled for far memory accesses and instead snoops remote sockets to check for ownership. Directory is used only for DRAM (near memory). |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.1(3), 4.2(1) |
All M5 servers and , C220 M7, C240 M7 , X210c M7, X410c M7 servers |
Disabled, Enabled
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Snoopy Mode for AD |
Enables snoop-mode for DCPMM accesses while maintaining directory on all DRAM accesses. Snoops maintain cache coherence between sockets. Directory reducessnoops by keeping the remote node information locally (in memory). Directory lookups and updates add memory traffic. Directory is a good tradeoff for DRAM, but not necessarily for DCPMM. For non-NUMA workload, when the feature is enabled, directory updates to DCPMM are eliminated, thereby helping DDRT bandwidth bound workloads. Directory is disabled for accesses to AD and instead snoops remote sockets to check for ownership. Directory is used only for DRAM accesses. |
4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.1(3), 4.2(1) |
All M5 servers and , C220 M7, C240 M7 , X210c M7, X410c M7 servers |
Disabled, Enabled
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Transparent Secure Memory Encryption |
Provides transparent hardware memory encryption of all data stored on system memory. |
4.1(3) |
C125 M5 servers |
Disabled, Enabled, Auto
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UMA Based Clustering |
As the name implies, UMA based clustering is the suggested clustering mode when the processor is configured as Uniform Memory Access (UMA) node, i.e. SNC is disabled. |
4.2(1) |
C220 M6, C240 M6, B200 M6, X210 M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disable-All-2All, Hemisphere-2-clusters, Quadrant-4-clusters
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Volatile Memory Mode |
Allows the memory mode configuration. |
4.0(2), 4.0(4), 4.1(1), 4.2(1), 5.0(1), 5.0(2) |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
1LM, 2LM
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Error Check Scrub |
Allows you to enable a memory device to perform memory checking, correction and count errors. |
4.0(2), 4.0(4), 4.1(1), 4.2(1), 5.0(1), 5.0(2) |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 |
Disabled, Enabled with result collection, Enabled without result collection |
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Rank Margin Tool |
Allows automated memory margin testing and is used to identify DDR margins at the rank level. |
4.0(2), 4.0(4), 4.1(1), 4.2(1), 5.0(1), 5.0(2) |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M6 |
Enable, Disable |
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Adaptive Refresh Management Level |
Selects Adaptive Refresh Management (ARFM) Level when refresh management (RFM) is required. |
4.0(2), 4.0(4), 4.1(1), 4.2(1), 5.0(1), 5.0(2) |
C220 M6, C240 M6, X210c M6 , C220 M7, C240 M7, X210c M7, X410c M7 |
Enable, Disable |