Number of Retries

Number of attempts to boot.

4.1(1) and later

Infinite. 13, 5

• Infinite—The system attempts all configured boot options and repeats until the system boots or is interrupted manually.

• 5, 13—The system attempts all configured boot options and repeats the selected number of times until the system boots or is interrupted. If all attempts fail, the system prompts to continue. Value 13 is the default value for Cisco UCS B200 M5 and 5 is the default value for Cisco UCS B480 M5.

Cool Down Time (sec)

The time to wait (in seconds) before the next boot attempt. This can be one of the following:

4.1(1) and later

15 sec, 45 sec, 90 sec

• 15, 45, 90—System waits for the selected time in seconds before the next boot attempt.

Boot Option Retry

Whether the BIOS retries NON-EFI based boot options without waiting for user input.

4.1(1) and later

Disabled, Enabled

• Disabled—Waits for user input before retrying NON-EFI based boot options.

• Enabled—Continually retries NON-EFI based boot options without waiting for user input.

Enables or disables IPv4 support for HTTP.

4.2(1) and later

Disabled, Enabled

• Disabled—IPv4 HTTP support is not available.

• Enabled—IPv4 HTTP support is made available.

IPV6 HTTP Support

4.2(1) and later

Disabled, Enabled

• Disabled—IPv6 HTTP support is not available.

• Enabled—IPv6 HTTP support is made available.

Enables or disables IPv4 support for PXE.

4.2(1) and later

Disabled, Enabled

• Disabled—IPv4 PXE support is not available.

• Enabled—IPv4 PXE support is made available.

Enables or disables IPv6 support for PXE.

4.2(1) and later

Disabled, Enabled

• Disabled—IPv6 PXE support is not available.

• Enabled—IPv6 PXE support is made available.

This option allows you to enable or disable the complete network style of the system.

4.1(1) and later

Disabled,Enabled

• Disabled—Network Stack support is not available.

• Enabled—Network Stack support is available.

Power ON Password

This token requires that you set a BIOS password before using the F2 BIOS configuration. If enabled, password needs to be validated before you access BIOS functions such as IO configuration, BIOS set up, and booting to an operating system using BIOS.

4.1(1) and later

Disabled, Enabled

• Disabled—Power On Password is disabled.

• Enabled—Power On Password is enabled.

P-SATA OptionROM

This options allows you to select the P-SATA mode.

4.1(1) and later

Disabled, LSI SW RAID, AHCI

• Disabled—P-SATA mode is disabled

• LSI SW RAID—Sets both SATA and sSATA controllers to RAID mode for LSI SW RAID.

• AHCI—The controller enables the Advanced Host Controller Interface (AHCI) and disables RAID.

SATA Mode

This options allows you to select the SATA mode.

4.1(1) and later

AHCI, LSISW RAID, Disabled

• Disabled—SATA mode is disabled

• LSI SW RAID—Sets both SATA and sSATA controllers to RAID mode for LSI SW RAID

• AHCI—The controller enables the Advanced Host Controller Interface (AHCI) and disables RAID.

VMD Enablement

Whether NVMe SSDs that are connected to the PCIe bus can be hot swapped. It also standardizes the LED status light on these drives. LED status lights can be optionally programmed to display specific Failure indicator patterns.

4.1(1) and later

Disabled, Enabled

• Disabled—Hot swap of NVMe SSDs that are connected to the PCIe bus is not allowed.

• Enabled—Hot swap of NVMe SSDs that are connected to the PCIe bus is allowed.

Intel VT for directed IO

Whether the processor uses Intel Virtualization Technology for Directed I/O (VT-d).

4.1(1) and later

Enabled, Disabled

• Disabled—The processor does not use virtualization technology.

• Enabled—The processor uses virtualization technology.

Intel(R) VT-d Coherency Support

Whether the processor supports Intel VT-d Coherency.

4.1(1) and later

Enabled, Disabled

• Disabled—The processor does not support coherency.

• Enabled—The processor uses VT-d Coherency as required.

Whether the processor supports Intel VT-d Address Translation Services (ATS).

4.1(1) and later

Disabled, Enabled

• Disabled—The processor does not support ATS.

• Enabled—The processor uses VT-d ATS as required.

PreBoot DMA Protection

4.3(6a)

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are Enabled.

ACS Control GPU n where n varies from 1-14

Access Control Services (ACS) allow the processor to enable or disable peer-to-peer communication between multiple devices for GPUs.

4.0(4) and later

Enabled, Disabled

• Disabled Disables peer-to-peer communication between multiple devices for GPUs.

• EnabledEnables peer-to-peer communication between multiple devices for GPUs.

CDN Support for LOM

Whether the Ethernet Networking Identifier naming convention is according to Consistent Device Naming (CDN) or the traditional way of naming conventions.

4.0(4) and later

Enabled, Disabled

• Disabled OS Ethernet Networking Identifier is named in a default convention as ETH0, ETH1 and so on.

• Enabled OS Ethernet Network Identifier is named in a consistent device naming (CDN) convention according to the physical LAN on Motherboard (LOM) port numbering; LOM Port 0, LOM Port 1 and so on.

External SSC Enable

This option allows you to Enable/Disable the Clock Spread Spectrum of the external clock generators.

4.1(2) and later

Enabled, Disabled, 0P3_Percent, 0P5_Percent, Hardware, Off

This option allows a downstream link to be disabled after an uncorrectable error, making recovery possible in a controlled and robust manner.

4.2(1) and later

Disabled, On fatal error, On fatal and non-fatal error

Whether Option ROM is available on the LOM port n

4.0(4) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

• UEFI only—The expansion slot is available only for UEFI.

• Legacy only—The expansion slot is available only for legacy.

Whether all PCIe PLL SSC ports are enabled or disabled.

4.1(2) and later

0–255 (Unit is (n/10)%)

This option allows you to restrict the maximum speed of MRAID.

4.0(2) and later

Auto, Disabled, GEN 1, GEN 2, GEN 3, GEN 4, GEN 5

• Disabled—The maximum speed is not restricted.

• Enabled—The maximum speed is restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed.

• GEN 3—8GT/s is the maximum speed allowed.

• GEN 4—16GT/s is the maximum speed allowed.

  Note	Applicable for M7, M8 servers only.

• GEN 5—32GT/s is the maximum speed allowed.

  Note	Applicable for M7, M8 servers only.

Whether Option ROM is available on the MRAID port.

4.0(2) and later

Disabled, Enabled

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available. .

Whether the server can use the Option ROMs present in the PCIe MSTOR RAID.

4.2(1) and later

Disabled, Enabled

• Disabled—Option ROM is not available.

• Enabled—Option ROM is available.

This option allows you to restrict the maximum speed of an NVME card installed in the PCIe slot.

4.0(2) and later

Disabled, Auto, GEN1, GEN2, GEN3, GEN4, GEN5

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

• GEN 4—16GT/s is the maximum speed allowed

• GEN 5—32GT/s is the maximum speed allowed

This options allows you to control the Option ROM execution of the PCIe adapter connected to the SSD:NVMe slot n.

4.0(2) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Link speed for PCIe Slot designated by slot n.

4.0(1) and later

Disabled, Auto, GEN1, GEN2, GEN3, GEN4, GEN5

GEN5 is supported only for speeds 1 to 6.

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

• GEN 4—16GT/s is the maximum speed allowed

• GEN 5—32 GT/s is the maximum speed allowed

To configure link speed for PCIe Slot:LOM.

4.0(1) and later

Disabled, Auto, GEN1, GEN2, GEN3

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

Whether Option ROM is available on the port.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

For C245 M8 platform, n ranges from 1 to 4.

This option allows you to restrict the maximum speed of an NVME card installed in the front PCIe slot.

4.0(4) and later

Disabled, Auto, GEN1, GEN2, GEN3, GEN4, GEN5

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

• GEN 4—16GT/s is the maximum speed allowed

• GEN 5—32GT/s is the maximum speed allowed

For C245 M8 platform, n ranges from 1 to 4.

This options allows you to control the Option ROM execution of the PCIe adapter connected to the SSD:NVMe slot n.

4.2(1) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

This option allows you to restrict the maximum speed of an adapter card installed in PCIe slot 1 and 2.

4.0(1) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

This option allows you to configure the Mezz state for PCIe slot.

4.0(1) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

• UEFI only—The expansion slot is available only for UEFI.

• Legacy only—The expansion slot is available only for legacy.

This option allows you to restrict the maximum speed of an MLOM adapter.

4.0 (1) and later

Auto, Disabled, GEN 1, GEN 2, GEN 3, GEN 4, GEN 5

• Disabled—The maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed.

• GEN 3—8GT/s is the maximum speed allowed.

• GEN 4—16GT/s is the maximum speed allowed.

• GEN 5—32GT/s is the maximum speed allowed.

Whether Option ROM is available on the MLOM port.

4.0(1) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

• UEFI only—The expansion slot is available only for UEFI.

• Legacy only—The expansion slot is available only for legacy.

This option allows you to restrict the maximum speed of MRAID.

4.0(2) and later

Auto, Disabled, GEN 1, GEN 2, GEN 3, GEN 4, GEN 5

• Disabled—The maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed.

• GEN 3—8GT/s is the maximum speed allowed.

• GEN 4—16GT/s is the maximum speed allowed.

• GEN 5—32GT/s is the maximum speed allowed.

Whether Option ROM is available on the MLOM port.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

Whether Option ROM is available on the port.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

This option allows you to restrict the maximum speed of RAID.

4.0(1) and later

Disabled, Auto, GEN1, GEN2, GEN3

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

Whether Option ROM is available on the RAID slot or not.

4.0(1) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

This option allows you to restrict the maximum speed of rear NVME.

4.0(4) and later

Auto, Disabled, GEN 1, GEN 2, GEN 3, GEN 4, GEN 5

• Disabled—The maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed.

• GEN 3—8GT/s is the maximum speed allowed.

• GEN 4—16GT/s is the maximum speed allowed.

• GEN 5—32GT/s is the maximum speed allowed.

Whether Option ROM is available on the rear NVME or not.

4.0(4) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

This option allows you to restrict the maximum speed of Riser.

4.0(4) and later

Disabled, Auto, GEN1, GEN2, GEN3

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

This option allows you to restrict the maximum speed of Riser in the x slot .

4.0(2) and later

Disabled, Auto, GEN1, GEN2, GEN3

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

Whether Option ROM is available on SAS slot or not.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

• UEFI only—The expansion slot is available only for UEFI.

• Legacy only—The expansion slot is available only for legacy.

This option allows you to restrict the maximum speed of Front SSD.

4.0(2) and later

Disabled, Auto, GEN1, GEN2, GEN3

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• GEN 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• GEN 2—5GT/s is the maximum speed allowed

• GEN 3—8GT/s is the maximum speed allowed

Re-Size BAR Support

Allows to enable or disable Re-sizable BAR support setup item.

4.3(4b) and later

Enabled, Disabled

PCIe Slots CDN Control where, CDN refers to Consistent Device Naming

PCIe Slots Consistent Device Naming (CDN) control allows PCIe slots to be named in a consistent manner. This makes PCIe slot names more uniform, easy to identify, and persistent when the configuration changes are made.

4.0(2) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

PCIe Slots Consistent Device Naming (CDN) control allows PCIe slots to be named in a consistent manner. This makes PCIe slot names more uniform, easy to identify, and persistent when the configuration changes are made.

4.0(2) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Enables or disables the ACPI SRAT SP Memory flag when the UEFI Memory Map Special Purpose Flag is enabled.

4.3(5b) and later

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

UEFI Memory Map Special Purpose Memory Flag

Changing the UEFI Memory Map Special knob settings impacts CXL cards on certain operating systems.

4.3(5b) and later

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

4.0(1) and later

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

Allows you to disable the PCI BME bit to mitigate the threat from an unauthorized external DMA

4.0(1), 4.0(2), 4.0(4), 4.1(1), 4.2(1), 4.3(4b). 4.3(5a)

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

MMIO High Granularity Size

Selects the allocation size that is used to assign memory-mapped I/O (MMIO) resources.

4.3(3c) and later

1G, 4G, 16G, 32G, 64G, 256G, 1024G, Auto

MMIO High Base

The base memory size according to memory-address mapping for the I/O (MMIO resources)

4.3(3c) and later

512G, 1T, 2T, 4T, 16T, 24T, 32T, 40T, 56T, Auto

Prevents DRAM and overall system BW drop in the presence of concurrent DCPMM BW saturating threads, with minimal impact to homogenous DDRT-only usages, Good for multi-tenant use cases, VMs, and so on. Targeted for App Direct, but also improves memory mode. Targets the “worst-case” degradations.

4.1(2) and later

Disabled, Recipe 1, Recipe 2, Recipe 3, Mode 0, Mode 1, Mode 2

• Disabled—Feature disabled.

• Recipe 1—6 modules, 4 modules per socket optimized

• Recipe 2—2 modules per socket optimized

• Recipe 3—1 module per socket optimized

• Mode 0—Disable the PMem QoS Feature

• Mode 1—M2M QoS Enable;CHA QoS Disable

• Mode 2— M2M QoS Enable; CHA QoS Enable

CR FastGo Config improves DDRT non-temporal write bandwidth when FastGO is disabled. When FastGO is enabled, it gives a faster flow of NT writes into the uncore, When FastGO is disabled, it lessens NT writes queueing up in the CPU uncore, thereby improving sequentially at DCPMM, resulting in improved bandwidth.

4.1(2) and later

Auto, Option 1—5, Enable Optimization, Disable Optimization

4.0(1) and later

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

To configure the refresh interval rate for internal memory.

4.0(1) and later

Auto, 1x Refresh, 2x Refresh, 3x, 4x

Extended asynchronous DRAM refresh (eADR) ensures that CPU caches lines with data are flushed at the right time and in the desired order and are also included in the power fail protected domain.

4.2(1) and later

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

Allows to boost the memory bandwidth.

4.2(1) and later

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

Limits the capacity in Partial Memory Mirror Mode up to 50 percent of the total memory capacity. The memory size can range from 0 GB to 65535 GB in increments of 1 GB.

4.0(2) and later

0 - 65535 with a step size of 1

Provides a protective mechanism to ensure the memory temperature is within the limits. When the temperature exceeds the maximum threshold value, the memory access rate is reduced and Baseboard Management Controllerf (BMC) adjusts the fan to cool down the memory to avoid DIMM damage due to overheat

4.0(1) and later

CLTT with PECI, Disabled

• Disabled—Options are Disabled.

• CLTT with PECI—Closed Loop Thermal Throttling (CLTT) with Platform Environment Control Interface (PECI).

Whether the BIOS supports NUMA.

4.0(1) and later

Enabled, Disabled

• Disabled—The BIOS does not support NUMA.

• Enabled—The BIOS includes the ACPI tables that are required for NUMA-aware operating systems. If you enable this option, the system must disable Inter-Socket Memory interleaving on some platforms.

enables efficient major mode arbitration between DDR and DDRT transactions on the DDR channel to optimize channel BW and DRAM latency.

4.0(2) and later

BW Optimized, Latency Optimized, Balanced Profile

• BW Optimized—Optimized for DDR and DDRT BW. This is the default option.

• Latency Optimized—Better DDR latency in the presence of DDRT BW. Available for M5 servers only.

• Balanced Profile—Optimized for Memory mode.

This option allows you to configure Operation Mode.

4.2(1) and later

Test-Only, Test and Repair

Controls the delayed refresh capability of the memory controller.

4.2(1) and later

High, Low

• High—The memory controller is allowed to postpone up to a maximum of eight refresh commands. The memory controller executes all the postponed refreshes within the refresh interval. For the ninth refresh command, the refresh priority becomes Panic and the memory controller pauses the normal memory transactions until all the postponed refresh commands are executed.

• Low—The memory controller is not allowed to postpone refresh commands.

  Note	It is recommended to leave this setting in the default state (Low) which will help to reduce susceptibility to Rowhammer-style attacks.

Partial cache line sparing (PCLS) is an error-prevention mechanism in memory controllers. PCLS statically encodes the locations of the faulty nibbles of bits into a sparing directory along with the corresponding data content for replacement during memory accesses.

4.2(1) and later

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

enables you to partially mirror by GB or by a percentage of the memory capacity. Depending on the option selected here, you can define either a partial mirror percentage or a partial mirror capacity in GB in available fields. You can partially mirror up to 50 percent of the memory capacity.

4.1(1) and later

Disabled, Percentage, Value in GB

• Disabled—Options are Disabled.

• Percentage—The amount of memory to be mirrored in the Partial Memory Mode is defined as a percentage of the total memory.

• Value in GB—The amount of memory to be mirrored in the Partial Memory Mode is defined in GB.

  Note	Partial Memory Mirror Mode is mutually exclusive to standard Mirroring Mode. Partial Mirrors 1-4 can be used in any number or configuration, provided they do not exceed the capacity limit set in GB or Percentage in the related options.

Limits the amount of available memory to be mirrored as a percentage of the total memory. This can range from 0.000.01 % to 50.00 % in increments of 0.01 %.

4.1(1) and later

0.00 - 50.00 with a step size of 0.01

Limits the amount of memory in Partial Mirrorn in GB. This can range from 0 GB to 65535 GB in increments of 1 GB.

4.1(1) and later

0 - 65535 with a step size of 1

4.0(1) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enabled—This option is enabled.

Runtime Post Package Repair

Enables the soft post-package repairs of the corrected memory errors during OS runtime.

4.3(4b) and later

How the memory reliability, availability, and serviceability (RAS) is configured for the server.

4.0(1) and later

Maximum Performance, Mirroring, Lockstep, Mirror Mode 1LM, Partial Mirror Mode 1LM, Sparing, ADDDC Sparing

• Maximum Performance—Optimizes the system performance and disables all the advanced RAS features.

• Mirroring—System reliability is optimized by using half the system memory as backup. This mode is used for UCS M4 and lower blade servers

• Lockstep—If the DIMM pairs in the server have an identical type, size, and organization and are populated across the SMI channels, you can enable lockstep mode to minimize memory access latency and provide better performance. Lockstep is enabled by default for B440 servers.

• Mirror Mode 1LM—Mirror Mode 1LM will set the entire 1LM memory in the system to be mirrored, consequently reducing the memory capacity by half. This mode is used for UCS M5 and M6 blade servers.

• Partial Mirror Mode 1LM—Partial Mirror Mode 1LM will set a part of the 1LM memory in the system to be mirrored, consequently reducing the memory capacity by half. This mode is used for UCS M5 and M6 blade servers.

• Sparing—System reliability is optimized by holding memory in reserve so that it can be used in case other DIMMs fail. This mode provides some memory redundancy, but does not provide as much redundancy as mirroring.

• ADDDC Sparing—System reliability is optimized by holding memory in reserve so that it can be used in case other DIMMs fail. This mode provides some memory redundancy, but does not provide as much redundancy as mirroring.

Post Package Repair (PPR) provides the ability to repair faulty memory cells by replacing them with spare cells.

4.1(1) and later

Disabled, Hard PPR

• Disabled—Options are Disabled.

• Hard PPR—This results in a permanent remapping of damaged storage cells.

Enables snoop-mode for DCPMM accesses while maintaining directory on all DRAM accesses. Snoops maintain cache coherence between sockets. Directory reduces snoops by keeping the remote node information locally (in memory). Directory lookups and updates add memory traffic

Directory is a good tradeoff for DRAM, but not necessarily for DCPMM. For non-NUMA workloads, when the feature is enabled, directory updates to DCPMM are eliminated, thereby helping DDRT bandwidth bound workloads. The directory is disabled for far memory accesses and instead snoops remote sockets to check for ownership. Directory is used only for DRAM (near memory).

4.0(1) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enabled—This option is enabled.

Enables snoop-mode for DCPMM accesses while maintaining directory on all DRAM accesses. Snoops maintain cache coherence between sockets. Directory reduces snoops by keeping the remote node information locally (in memory). Directory lookups and updates add memory traffic.

Directory is a good tradeoff for DRAM, but not necessarily for DCPMM. For non-NUMA workloads, when the feature is enabled, directory updates to DCPMM are eliminated, thereby helping DDRT bandwidth bound workloads. The directory is disabled for accesses to AD and instead snoops remote sockets to check for ownership. Directory is used only for DRAM accesses.

4.0(1) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enabled—This option is enabled.

As the name implies, UMA based clustering is the suggested clustering mode when the processor is configured as Uniform Memory Access (UMA) node, i.e. SNC is disabled.

4.2(1) and later

Disable-All-2All, Hemisphere-2-clusters, Quadrant-4-clusters

Allows the memory mode configuration.

4.0(2) and later

1LM, 2LM

• 1LM—Configures 1 Layer Memory(1LM).This is the default value for M7 servers.

• 2LM—Configures 2 Layer Memory(1LM).

Error Check Scrub

Allows you to enable a memory device to perform memory checking, correction and count errors.

4.0(2) and later

Disabled, Enabled with result collection, Enabled without result collection

Rank Margin Tool

Allows automated memory margin testing and is used to identify DDR margins at the rank level.

4.0(2) and later

Enabled, Disabled

Adaptive Refresh Management Level

Selects Adaptive Refresh Management (ARFM) Level when refresh management (RFM) is required.

4.0(2) and later

Whether to enable or disable memory mapped I/O of 64-bitPCI devices to 4GB or greater address space. Legacy option ROMs are not able to access addresses above 4GB. PCI devices that are 64-bit compliant but use a legacy option ROM may not function correctly with this setting enabled.

4.0(1) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This options is enabled.

Allows you to set the priority for VGA graphics devices if multiple VGA devices are found in the system.

4.0(2) and later

Offboard, Onboard, Onboard VGA Disabled

• Onboard—Priority is given to the onboard VGA device. BIOS post screen and OS boot are driven through the onboard VGA port

• Offboard——Priority is given to thePCIE Graphics adapter. BIOS post screen and OS boot are driven through the external graphics adapter port.

• Onboard VGA Disabled —Priority is given to the PCIE Graphics adapter, and the onboard VGA device is disabled

  Note	The vKVM does not function when the onboard VGA is disabled.

Automatically varies processor speed and power usage based on processor utilization to increase performance per watt. Most effective under moderate utilization.

4.3(2) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This options is enabled.

If enabled, CPU automatically demotes to C1 based on un-core auto-demote information.

4.0(2) and later

Disabled, Enabled, Auto

• Disabled—This option is Disabled.

• Enable—This options is enabled.

Select whether to enable processors to automatically undemote from C1.

4.0(2) and later

Disabled, Enabled, Auto

• Disabled—This option is Disabled.

• Enable—This options is enabled.

Enhanced CPU Performance

Enhances CPU performance by adjusting server settings automatically.

4.0(2) and later

Disabled, Auto

• Disabled—This option is Disabled.

• Auto—Allows to adjust server settings to increase the processor performance.

In CPU non-inclusive cache scheme, Mid-Level Cache (MLC) evictions are filled into the Last-Level Cache (LLC). When lines are evicted from the MLC, the core can flag them as dead (not likely to be read again). The LLC has the option to drop dead lines and not fill them in the LLC.

4.0(2) and later

Disabled, Enabled, Auto

• Disabled—The dead lines are always dropped and are never filled into the LLC.

• Enable—Allows the LLC to fill dead lines into the LLC if there is free space available. This is the default option.

• Auto—The CPU determines the LLC dead line allocation.

Enables the number of Ultra Path Interconnect (UPI) links required by the processor.

4.0(2) and later

Auto, 1, 2, 3

The UPI power management can be used for conserving power on the server.

4.0(2) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This options is enabled.

This feature allows an LLC request to be duplicated and sent to an appropriate memory controller in a remote machine based on the recent LLC history to reduce latency.

4.0(2) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This options is enabled.

• Auto—The CPU determines the functionality.

Latency Optimized Mode

A set of BIOS settings that prioritize low latency and consistent performance over energy efficiency or other optimizations.

4.3(6a)

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

QPI Link Frequency Select

4.0(4) and later

Auto, 9.6 GT/s, 10.4 GT/s, 11.2GT/s, 12.8GT/s, 14.4GT/s, 16.0GT/s, 20.0GT/s, 16.0GT/s, 20.0GT/s,24.0GT/s, Auto, Use Per Link Setting

Whether the system supports legacy USB devices.

4.2(1) and later

Auto,Enabled, Disabled

Whether the front panel USB devices are enabled or disabled.

4.2(1) and later

Enabled, Disabled

Whether the internal USB devices are enabled or disabled.

4.2(1) and later

Enabled, Disabled

Whether the USB Port KVM devices are enabled or disabled.

4.2(1) and later

Enabled, Disabled

Whether the USB port rear devices are enabled or disabled.

4.2(1) and later

Enabled, Disabled

Whether the SD card drives are enabled or disabled.

4.2(1) and later

Enabled, Disabled

Processor Reserved Memory Range Registers (PRMRR) is the size of the protected region in the system DRAM.

4.3(2) and later

Invalid Config, 1G, 2G, 4G, 8G, 16G, 32G, 64G, 128G, 256G, 512G, 128M, Auto, 256M, 512M

Whether the processor fetches cache lines in even/odd pairs instead of fetching just the required line.

4.0(2) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This option is enabled.

Enables CPU Autonomous C-State, which converts the HALT instructions to the MWAIT instructions.

4.0(2) and later

Disabled, Enabled

Allows the user to select the BIOS performance state that is set before the operating system handoff.

4.0(2) and later

DFX OSB

Controls the Opportunistic Snoop Broadcast (OSB) feature. OSB is used by CHA to broadcast snoops under lightly loaded ring or Intel UPI link condition. It is used to reduce the latency due to the directory lookup.

Auto, Enabled, Disabled

Allows the CPU to trigger interrupts on corrected machine check events. The corrected machine check interrupt (CMCI) allows faster reaction than the traditional polling timer.

4.0(2) and later

Disabled, Enabled

Allows you to set a customized value for Thermal Design Power (TDP).

4.0(2) and later

Normal, Level 1, Level 2

Sets the state of logical processor cores per CPU in a package. If you choose All as the value, Intel Hyper Threading technology is also enabled.

4.0(2) and later

All, 1 through 86

• All— Enables multiprocessing on all logical processor cores.

• 1 through 86—Specifies the number of logical processor cores per CPU that can run on the server. To disable multiprocessing and have only one logical processor core per CPU running on the server, choose 1.

  Note	For M6 servers, it ranges from 1 through 48.

  Note	1, 2, and 3 options are not applicable for M8 servers.

  Note	From 65 to 86 is applicable for M8 servers only.

  Note	From 1 to 64 is applicable for M7 servers only.

Allows you to determine whether system performance or energy efficiency is more important on this server.

4.0(2) and later

Performance, Balanced Performance, Balanced power, power

CPU performance by adjusting server settings automatically.

4.0(2) and later

Disabled, Enabled

When energy efficient turbo is enabled, the optimal turbo frequency of the CPU turns dynamic based on CPU utilization. The power/performance bias setting also influences the energy efficient turbo.

4.0(2) and later

Disabled, Enabled

Whether the processor uses Enhanced Intel SpeedStep Technology, which allows the system to dynamically adjust processor voltage and core frequency. This technology can result in decreased average power consumption and decreased average heat production.

4.0(2) and later

Disabled, Enabled

Allows you to determine whether system performance or energy efficiency is more important on this server.

4.0(2) and later

Disabled, Enabled

Allows you to determine whether system performance or energy efficiency is more important on this server.

4.0(2) and later

Performance, Balanced Performance, Balanced power, power

Classifies memory areas on the server to specify where the application code can execute. As a result of this classification, the processor disables code execution if a malicious worm attempts to insert code in the buffer. This setting helps to prevent damage, worm propagation, and certain classes of malicious buffer overflow attacks.

4.0(2) and later

Disabled, Enabled

IOAT Configuration

Enables or disables the CPM (Content Processing Module) in IOAT (Intel® I/O Acceleration Technology) accelerators.

4.3(3c) and later

Disabled, Enabled

Allows you to set the type of Advanced Processor Interrupt controller (APIC) architecture.

4.0(2) and later

Disabled, Enabled

Whether the processor allows the Intel hardware prefetcher to fetch streams of data and instructions from memory into the unified second-level cache when necessary.

4.0(2) and later

Disabled, Enabled

Enables processor Hardware Power Management (HWPM).

4.0(2) and later

Disabled, HWPM Native Mode, HWPM OOB Mode, Native Mode with no Legacy

This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs).

4.0(2) and later

Auto, 1-way Interleave, 2-way Interleave

Intel Dynamic Speed Select modes allow you to run the CPU with different speeds and cores in auto mode.

4.0(2) and later

Disabled, Enabled

Whether the processor uses Intel Hyper-Threading Technology, which allows multithreaded software applications to execute threads in parallel within each processor.

4.0(2) and later

Disabled, Enabled

Whether the processor uses Intel Turbo Boost Technology, which allows the processor to automatically increase its frequency if it is running below power, temperature, or voltage specifications.

4.0(2) and later

Disabled, Enabled

Whether the processor uses Intel Virtualization Technology for Directed I/O (VT-R)

4.0(2) and later

Disabled, Enabled

Whether the processor uses the DCU IP Prefetch mechanism to analyze historical cache access patterns and preload the most relevant lines in the L1 cache.

4.0(2) and later

Disabled, Enabled

KTI prefetch is a mechanism to get the memory read started early on a DDR bus.

4.0(2) and later

Disabled, Enabled, Auto

Whether the processor uses the LLC Prefetch mechanism to fetch the date into the LLC.

4.0(2) and later

Disabled, Enabled

The amount of power available to the server components when they are idle.

4.0(2) and later

No Limit, Auto, C0 C1 State, C2, C6 Non Retention, C6 Retention

It sets the interval for a full memory scan.

4.0(2) and later

Disabled, Enabled

• Enable—The system periodically reads and writes memory searching for ECC errors. If any errors are found, the system attempts to fix them. This option may correct single bit errors before they become multi-bit errors, but it may adversely affect performance when the patrol scrub is running.

• Disable—The system checks for memory ECC errors only when the CPU reads or writes a memory address.

It sets the interval for a full memory scan.

4.0(2) and later

Enabled, Disabled, Enable at End of POST

• Enable—The system periodically reads and writes memory searching for ECC errors. If any errors are found, the system attempts to fix them. This option may correct single bit errors before they become multi-bit errors, but it may adversely affect performance when the patrol scrub is running.

• Disable—The system checks for memory ECC errors only when the CPU reads or writes a memory address.

Allows the processor to transition to its minimum frequency upon entering C1. This setting does not take effect until after you have rebooted the server.

4.0(2) and later

Disabled, Enabled

Whether the processor sends the C6 report to the operating system.

4.0(2) and later

Disabled, Enabled

Allows you to define how BIOS communicates the P-state support model to the operating system. There are 3 models as defined by the Advanced Configuration and Power Interface (ACPI) specification.

4.0(2) and later

SW All, HW All, SW Any

Determines if the BIOS or Operating System can turn on the energy performance bias tuning. The options are BIOS and operating system.

4.0(2) and later

BIOS, OS, PECI

Allows you to select different UPI link frequency running.

4.0(2) and later

Auto, 9.6GT/S, 10.4GT/S, 11.2GT/S, 12.8GT/s, 14.4GT/s, 16.0GT/s, 20.0GT/s, 24.0GT/s, Use Per Link Setting

Whether the CPU supports sub NUMA clustering, in which the tag directory and the memory channel are always in the same region.

4.0(2) and later

Disabled, Enabled, Auto, SNC2, SNC4

Whether the processor uses the DCU IP Prefetch mechanism to analyze historical cache access patterns and preload the most relevant lines in the L1 cache.

4.0(2) and later

Disabled, Enabled, Auto

Allows you to configure the scaling of the uncore frequency of the processor.

4.0(2) and later

Disabled, Enabled, Mode 0, and Mode 1

Uncore Frequency Scaling IO

Adjusts the frequency of processor uncore components responsible for I/O operations to optimize power and performance.

6.0(1a.0) and later

Mode 1, Mode 0

This feature allows for workload optimization.

4.0(2) and later

Balanced, IO Sensitive

Whether XPT prefetch is used to enable a read request that is sent to the last level cache to issue a copy of that request to the memory controller prefetcher.

4.0(2) and later

Auto, Disabled, Enabled

X2APIC Opt-Out Flag

Prevents the operating system from enabling extended xAPIC (x2APIC) mode when the OS is not working with x2APIC.

4.2(3) and later

Disabled, Enabled

Intel Speed Select

Allows you to adjust different cores to operate in different frequencies to have a better power efficiency.

The values Config 1 and Config 2 are not supported on Cisco UCS M6 and M7 servers.

For Cisco UCS M6 and Cisco UCS M7 servers, the values Config 3 and Config 4 (4th Gen Intel Xeon Scalable processors and 5th Gen Intel Xeon Scalable processors) are equivalent to the values Config 1 and Config 2 (3rd Gen Intel Xeon Scalable processors).

4.0(2) and later

Auto, Base, Config 1, Config 2, Config 3, Config 4

• Config 1 and Config 2 are options available for M5 servers only with Base as the default.

• Auto is the default for M8.

IIO eDPC Support

The eDPC (Enhanced Downstream Port Containment) allows a downstream link to be disabled after an uncorrectable error, enabling recovery possible in a controlled and robust manner. This can be one of the following:

4.3(6c) and later

Disabled, On Fatal Error, On Fatal and Non-Fatal Errors

• Disabled—eDPC support is turned off, and the system does not take any action to disable downstream links in response to errors.

• On Fatal Error—eDPC is enabled only for fatal errors.is not supported on Cisco UCS C225 M8, Cisco UCS C245 M8, and X215c M8 servers.

• On Fatal and Non-Fatal Errors—eDPC is enabled for both fatal and non-fatal errors.

What Baud rate is used for the serial port transmission speed. If you disable Console Redirection, this option is not available.

4.2(1) and later

9.6k, 19.2k, 38.4k, 57.6k, 115.2k

Consistent Device Naming allows Ethernet interfaces to be named in a consistent manner. This makes Ethernet interface names more uniform, easy to identify, and persistent when adapter or other configuration changes are made.

4.2(1) and later

Enabled, Disabled

When this token is enabled, the BIOS saves the memory training results (optimized timing/voltage values) along with CPU/memory configuration information and reuses them on subsequent reboots to save boot time. The saved memory training results are used only if the reboot happens within 24 hours of the last save operation.

4.2(1) and later

Enabled, Disabled

This option denotes the type of messages in BIOS tech log file.

4.2(1) and later

Maximum, Minimum, Normal

• Maximum—Critical messages will be displayed in the log file. This is the default option

• Minimum—Warning and loading messages will be displayed in the log file.

• Normal—Normal and information related messages will be displayed in the log file.

The Option ROM launch is controlled at the PCI Slot level, and is enabled by default. In configurations that consist of a large number of network controllers and storage HBAs having Option ROMs, all the Option ROMs may get launched if the PCI Slot Option ROM Control is enabled for all. However, only a subset of controllers may be used in the boot process. When this token is enabled, Option ROMs are launched only for those controllers that are present in boot policy.

4.2(1) and later

Enabled, Disabled

Allows a serial port to be used for console redirection during POST and BIOS booting. After the BIOS has booted and the operating system is responsible for the server, console redirection is irrelevant and has no effect

4.2(1) and later

Disabled, COM 0, COM 1

• COM 0 enables serial port for console redirection during POST. This option is valid only for M6 blade servers and rack-mount servers.

• COM 1 or serial-port-b enables serial port B for console redirection and allows it to perform server management tasks. This option is only valid for rack-mount servers.

Whether a handshake protocol is used for flow control. Request to Send / Clear to Send (RTS/CTS) helps to reduce frame collisions that can be introduced by a hidden terminal problem.

4.2(1) and later

None, RTC-CTS

Whether the FRB2 timer is used for recovering the system if it hangs during POST.

4.2(1) and later

Enabled, Disabled

Whether the BIOS programs the watchdog timer with a predefined timeout value. If the operating system does not complete booting before the timer expires, the CIMC resets the system and an error is logged.

4.2(1) and later

Enabled, Disabled

What action the system takes if the watchdog timer expires.

4.2(1) and later

Power-off, Reset

What timeout value the BIOS uses to configure the watchdog timer.

4.2(1) and later

5 minutes, 10 minutes, 15 minutes, 20 minutes

What type of character formatting is used for console redirection.

4.2(1) and later

PC-ANSI, VT100, VT100-PLUS, VT-UTF8

MK-TME allows you to have multiple encryption domains with one with own key. Different memory pages can be encrypted with different keys.

4.2(1) nnd later

Enabled, Disabled

Allows you to enable Software Guard Extensions(SGX) feature.

4.2(1) and later

Enabled, Disabled

Allows you to provide the capability to encrypt the entirety of the physical memory of a system.

4.2(1) and later

Enabled, Disabled

Allows you to change the seed for the security key used for the locked memory region that is created.

4.2(1) and later

SGX Owner EPOCH activated, Change to New Random Owner EPOCHs, Manual User Defined Owner EPOCHs, SGX Owner EPOCH deactivated

Allows you to enable the registration authority service to store the platform keys.

4.2(1) and later

Enabled, Disabled

Allows you to define the SGX EPOCH owner value for the EPOCH number designated by 0.

4.2(1) and later

0 - ffffffffffffffff with a step size of 1

Allows you to define the SGX EPOCH owner value for the EPOCH number designated by 1.

4.2(1) and later

0 - ffffffffffffffff with a step size of 1

Allows the system to perform SGX factory reset on subsequent boot.

4.2(1) and later

Enabled, Disabled

Allows you to set the Software Guard Extensions (SGX) value.

4.2(1) and later

SGX PUBKEY HASH0, SGX PUBKEY HASH1, SGX PUBKEY HASH2, SGX PUBKEY HASH3

• SGX PUBKEY HASH0—Between 7-0.

• SGX PUBKEY HASH1—Between 15-8.

• SGX PUBKEY HASH2—Between 23-16.

• SGX PUBKEY HASH3—Between 31-24.

Allows you to enable SGX Write feature.

4.2(1) and later

Enabled, Disabled

Allows you to enable SGX Package Info In-Band Access.

4.2(1) and later

Enabled, Disabled

Allows you to enable SGX QoS.

4.2(1) and later

Enabled, Disabled

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 1 or SHA-1 PCR Bank allows to enable or disable TPM security.

4.2(1) and later

Enabled, Disabled

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 256-bit or SHA-256PCR Bank allows to enable or disable TPM security.

4.2(1) and later

Enabled, Disabled

SHA384 PCR Bank

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 384-bit or SHA-384PCR Bank allows to enable or disable TPM security.

4.3(3a) and later

Enabled, Disabled

Whether to enable or disable the Trusted Platform Module (TPM), which is a component that securely stores artifacts that are used to authenticate the server.

4.2(1) and later

Enabled, Disabled

Trust Domain Extension

Whether to enable or disable the Trust Domain Extension (TDX), which protects the sensitive data and applications from unauthorized access.

4.3(3a) and later

Enabled, Disabled

TDX Secure Arbitration Mode (SEAM) Loader

Whether to enable or disable the TDX Secure Arbitration Mode (SEAM) Loader, which helps to verify the digital signature on the Intel TDX module and load it into the SEAM-memory range.

4.3(3a) and later

TDX Secure Arbitration Mode (SEAM) Loader

Trusted Platform Module (TPM) Pending Operation option allows you to control the status of the pending operation.

4.2(1) and later

None, TpmClear

Whether to enable or disable TPM Minimal Physical Presence, which enables or disables the communication between the OS and BIOS for administering the TPM without compromising the security.

4.2(1) and later

Enabled, Disabled

Whether to enable or disable Intel Trusted Execution Technology (TXT), which provides greater protection for information that is used and stored on the business server.

4.2(1) and later

Enabled, Disabled

Security Device Support

It controls the entire TPM functionality.

4.2(3) and later

Enabled, Disabled

DMA Control Opt-In Flag

Enabling this token enables Windows 2022 Kernel DMA Protection feature. The OS treats this as a hint that the IOMMU should be enabled to prevent DMA attacks from possible malicious devices.

4.2(2) and later

Enabled, Disabled

LIMIT CPU PA to 46 Bits

Limits CPU physical address to 46 bits to support the older Hyper-v CPU platform.

4.2(2) and later

Enabled, Disabled

GPU Direct CPU1

When enabled, ACS is disabled for GPUs on the specified CPU in systems using the UCXS-580P.

Enabled, Disabled

GPU Direct CPU2

When enabled, ACS is disabled for GPUs on the specified CPU in systems using the UCXS-580P.

6.0(1.250229)

Enabled, Disabled

GPU Direct CPU3

When enabled, ACS is disabled for GPUs on the specified CPU in systems using the UCXS-580P.

6.0(2x)

Enabled, Disabled

GPU Direct CPU4

When enabled, ACS is disabled for GPUs on the specified CPU in systems using the UCXS-580P.

6.0(2x)

Enabled, Disabled

Name

Description

Versions

Values

IPV4 HTTP Support

Enables or disables IPv4 support for HTTP.

4.2(1) and later

Disabled, Enabled

• Disabled—IPv4 HTTP support is not available.

• Enabled—IPv4 HTTP support is made available.

IPV6 HTTP Support

4.2(1) and later

Disabled, Enabled

• Disabled—IPv6 HTTP support is not available.

• Enabled—IPv6 HTTP support is made available.

Enables or disables IPv4 support for PXE.

4.2(1) and later

Disabled, Enabled

• Disabled—IPv4 PXE support is not available.

• Enabled—IPv4 PXE support is made available.

Enables or disables IPv6 support for PXE.

4.2(1) and later

Disabled, Enabled

• Disabled—IPv6 PXE support is not available.

• Enabled—IPv6 PXE support is made available.

This option allows you to enable or disable the complete network style of the system.

4.1(1) and later

Disabled,Enabled

• Disabled—Network Stack support is not available.

• Enabled—Network Stack support is available.

Power ON Password

This token requires that you set a BIOS password before using the F2 BIOS configuration. If enabled, password needs to be validated before you access BIOS functions such as IO configuration, BIOS set up, and booting to an operating system using BIOS.

4.1(1) and later

Disabled, Enabled

• Disabled—Power On Password is disabled.

• Enabled—Power On Password is enabled.

Whether all ARI support ports are enabled or disabled.

4.2(1) and later

Disabled, Enabled, Auto

• Disabled—This option is Disabled.

• Enabled—This options is enabled.

• Auto—PCIe ARI Support is in auto mode.

This option allows you to restrict the maximum speed of MRAID.

4.0(2) and later

Auto, Disabled, Gen 1, Gen 2, Gen 3, Gen 4, Gen 5

• Disabled—The maximum speed is not restricted.

• Enabled—The maximum speed is restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed.

• Gen 3—8GT/s is the maximum speed allowed.

• Gen 4—16GT/s is the maximum speed allowed.

  Note	Applicable for M7, M8 servers only.

• Gen 5—32GT/s is the maximum speed allowed.

  Note	Applicable for M7, M8 servers only.

This option allows you to restrict the maximum speed of an MSTOR adapter.

4.2(1) and later

Auto, Disabled, Gen 1, Gen 2, Gen 3, Gen 4, Gen 5

• Disabled—The maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed.

• Gen 3—8GT/s is the maximum speed allowed.

• Gen 4—16GT/s is the maximum speed allowed.

• Gen 5—32GT/s is the maximum speed allowed.

  Note	Applicable for M8 servers only.

Whether the server can use the Option ROMs present in the PCIe MSTOR RAID.

4.2(1) and later

Disabled, Enabled

• Disabled—Option ROM is not available.

• Enabled—Option ROM is available.

This option allows you to restrict the maximum speed of an NVME card installed in the PCIe slot.

4.0(2) and later

Disabled, Auto, GEN1, GEN2, GEN3, GEN4, GEN5

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed

• Gen 3—8GT/s is the maximum speed allowed

• Gen 4—16GT/s is the maximum speed allowed

• Gen 5—32GT/s is the maximum speed allowed

This options allows you to control the Option ROM execution of the PCIe adapter connected to the SSD:NVMe slot n.

4.0(2) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Link speed for PCIe Slot designated by slot n.

4.0(1) and later

Disabled, Auto, GEN1, GEN2, GEN3, GEN4, GEN5

GEN5 is supported only for speeds 1 to 6.

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed

• Gen 3—8GT/s is the maximum speed allowed

• Gen 4—16GT/s is the maximum speed allowed

• Gen 5—32 GT/s is the maximum speed allowed

This option allows you to restrict the maximum speed of an MLOM adapter.

4.0 (1) and later

Auto, Disabled, Gen 1, Gen 2, Gen 3, Gen 4, Gen 5

• Disabled—The maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed.

• Gen 3—8GT/s is the maximum speed allowed.

• Gen 4—16GT/s is the maximum speed allowed.

• Gen 5—32GT/s is the maximum speed allowed.

Whether Option ROM is available on the MLOM port.

4.0 (1) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

• UEFI only—The expansion slot is available only for UEFI.

• Legacy only—The expansion slot is available only for legacy.

This option allows you to restrict the maximum speed of MRAID.

4.0(2) and later

Auto, Disabled, Gen 1, Gen 2, Gen 3, Gen 4, Gen 5

• Disabled—The maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed.

• Gen 3—8GT/s is the maximum speed allowed.

• Gen 4—16GT/s is the maximum speed allowed.

• Gen 5—32GT/s is the maximum speed allowed.

Whether Option ROM is available on the MLOM port.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

Whether Option ROM is available on the port.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

For C245 M8 platform, n ranges from 1 to 4.

This option allows you to restrict the maximum speed of an NVME card installed in the front PCIe slot.

4.0(4) and later

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed

• Gen 3—8GT/s is the maximum speed allowed

• Gen 4—16GT/s is the maximum speed allowed

• Gen 5—32GT/s is the maximum speed allowed

For C245 M8 platform, n ranges from 1 to 4.

This options allows you to control the Option ROM execution of the PCIe adapter connected to the SSD:NVMe slot n.

4.2(1) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Whether Option ROM is available on the port.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

This option allows you to restrict the maximum speed of rear NVME.

4.0(4) and later

Auto, Disabled, Gen 1, Gen 2, Gen 3, Gen 4, Gen 5

• Disabled—The maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed.

• Gen 3—8GT/s is the maximum speed allowed.

• Gen 4—16GT/s is the maximum speed allowed.

• Gen 5—32GT/s is the maximum speed allowed.

Whether Option ROM is available on the rear NVME or not.

4.0(4) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

This option allows you to restrict the maximum speed of Riser in the x slot .

4.0(2) and later

Disabled, Auto, GEN1, GEN2, GEN3

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed

• Gen 3—8GT/s is the maximum speed allowed

Whether Option ROM is available on SAS slot or not.

4.0(2) and later

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

• UEFI only—The expansion slot is available only for UEFI.

• Legacy only—The expansion slot is available only for legacy.

This option allows you to restrict the maximum speed of Front SSD.

4.0(2) and later

Disabled, Auto, GEN1, GEN2, GEN3

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed

• Gen 3—8GT/s is the maximum speed allowed

Single Root I/O Virtualization (SR-IOV) Support

4.3(4b) and later

Enabled, Disabled

Re-Size BAR Support

Allows to enable or disable Re-sizable BAR support setup item.

4.3(4b) and later

Enabled, Disabled

PCIe Slots CDN Control where, CDN refers to Consistent Device Naming

PCIe Slots Consistent Device Naming (CDN) control allows PCIe slots to be named in a consistent manner. This makes PCIe slot names more uniform, easy to identify, and persistent when the configuration changes are made.

4.0(2) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

PCIe Slots Consistent Device Naming (CDN) control allows PCIe slots to be named in a consistent manner. This makes PCIe slot names more uniform, easy to identify, and persistent when the configuration changes are made.

4.0(2) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

UEFI Memory Map Special Purpose Memory Flag

Changing the UEFI Memory Map Special knob settings impacts CXL cards on certain operating systems.

4.3(5b) and later

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

4.0 (1) and later

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

Allows you to disable the PCI BME bit to mitigate the threat from an unauthorized external DMA

4.0 (1), 4.0(2), 4.0(4), 4.1(1), 4.2(1), 4.3(4b). 4.3(5a)

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Allows the memory controller to defer the refresh cycles when the memory is active and accomplishes the refresh within a specified window. The deferred refresh cycles may run in a burst of several refresh cycles.

4.0 (1) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Input Output Memory Management Unit(IOMMU) allows AMD processors to map virtual addresses to physical addresses.

4.0(2) and later

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

Determines how physical addresses are assigned to applications.

4.0 (1) and later

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

Whether memory blocks across the DRAM chip selects for node 0 are interleaved.

4.2(1) and later

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

DRAM Scrub Time

The value that represents the number of hours to scrub the whole memory.

4.3(4a) and later

Disabled, 1 hour, 4 hours, 6 hours, 8 hours, 12 hours, 16 hours, 24 hours, 48 hours, Auto

This option selects the operating mode of the Secured Nested Paging (SNP) Memory and the reverse Map Table (RMP). The RMP is used to ensure a one-to-one mapping between system physical addresses and guest physical addresses.

4.2(1) and later

Disabled, Enabled, Auto, Custom

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

• Custom—Options are customized.

Allows you to configure SNP memory size.

Allows you to configure the number of NUMA (Non-Uniform Memory Access) nodes per CPU socket.

4.2(1) and later

Auto, NPS0, NPS1, NPS2, NPS4

• NPS0—Zero NUMA node per socket.

• NPS1—One NUMA node per socket.

• NPS2—Two NUMA nodes per socket.

• NPS4—Four NUMA nodes per socket.

• Auto—Number of channels are set to auto.

Determines the memory blocks to be interleaved. It also determines the starting address of the interleave (bit 8, 9, 10 or 11).

4.0(2) and later

Auto, Channel, Die, none, Socket, Disabled, Enabled

• Avaialble options for M5:Auto, Channel, Die, none, Socket

• Avaialble options for M6:Auto, Disabled

• Avaialble options for M8:Auto, Enabled, Disabled

Determines the size of the memory blocks to be interleaved. It also determines the starting address of the interleave (bit 8, 9, 10 or 11).

4.0(2) and later

1 KB, 2 KB, 4KB, 256 Bytes, 512 Bytes, Auto

Allows you to enable the Secure Nested Paging feature.

4.2(1) and later

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

To configure the refresh interval rate for internal memory.

4.0 (1) and later

Auto, 1x Refresh, 2x Refresh, 3x, 4x

To configure DRAM SW thermal throttling.

4.0 (1) and later

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

Post Package Repair (PPR) provides the ability to repair faulty memory cells by replacing them with spare cells.

4.2(1) and later

Disabled, Hard PPR

• Disabled—This option is Disabled.

• Hard PPR—This results in a permanent remapping of damaged storage cells.

Runtime Post Package Repair

Enables the soft post-package repairs of the corrected memory errors during OS runtime.

4.3(4b) and later

Disabled, Enabled

Enables running encrypted virtual machines (VMs) in which the code and data of the VM are isolated.

4.2(1) and later

253 ASIDs, 509 ASIDs, Auto

• 253 ASIDs

• 509 ASIDs

• Auto

  Note	It is recommended to leave this setting in the default state of Auto to mitigate Rowhammer-style attacks.

Whether the processor uses the Secure Memory Encryption Enable (SMEE) function, which provides memory encryption support.

4.0(4) and later

Disabled, Enabled, Auto

• Disabled—This option is Disabled.

• Enabled—This option is enabled.

• Auto—This option is set to auto mode.

Provides transparent hardware memory encryption of all data stored on system memory.

4.1(3) and later

Disabled, Enabled, Auto

• Disabled—This option is Disabled.

• Auto—This option is set to auto mode.

Whether to enable or disable memory mapped I/O of 64-bitPCI devices to 4GB or greater address space. Legacy option ROMs are not able to access addresses above 4GB. PCI devices that are 64-bit compliant but use a legacy option ROM may not function correctly with this setting enabled.

4.0 (1) and later

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This options is enabled.

Allows you to set the priority for VGA graphics devices if multiple VGA devices are found in the system.

4.0(2) and later

Offboard, Onboard, Onboard VGA Disabled

• Onboard—Priority is given to the onboard VGA device. BIOS post screen and OS boot are driven through the onboard VGA port

• Offboard——Priority is given to thePCIE Graphics adapter. BIOS post screen and OS boot are driven through the external graphics adapter port.

• Onboard VGA Disabled —Priority is given to the PCIE Graphics adapter, and the onboard VGA device is disabled

  Note	The vKVM does not function when the onboard VGA is disabled.

Whether the AMD processor increases its frequency on some cores when it is idle or not being used much

4.0(2) and later

Disabled, Auto

• Disabled—This option is Disabled.

• Auto—The CPU automatically determines how to boost performance.

Whether the AMD processors control IO-based C-state generation and DF C-states.

4.0(2) and later

Auto, Disabled, Enabled

• Auto—This options is set to auto mode.

• Disabled—This option is Disabled.

• Enable—This options is enabled.

Whether the processor allows the AMD hardware prefetcher to speculatively fetch streams of data and instruction from memory into the L1 or L2 cache when necessary.

Applicable for C125 M5, C225 M6, C245 M6, C225 M8, C245 M8, and X215c M8 platforms only.

4.0(2) and later

Auto, Disabled, Enabled

• Auto—This options is set to auto mode.

• Disabled—This option is Disabled.

• Enable—This options is enabled.

Allows AMD processors to determine how to operate.

4.0(2) and later

Auto, Performance, Power

• Auto—The CPU automatically uses default power determinism settings.

• Performance—Processor operates at the best performance in a consistent manner.

• Power—Processor operates at the maximum allowable performance on a per die basis.

Allows you to configure power consumption based on efficiency.

4.0(2) and later

Auto, Enabled

• Enabled—This option is enabled.

• Auto—The CPU automatically uses default settings.

Allows you to configure Collaborative Processor Performance Control.

4.0(2) and later

Auto, Disabled, Enabled

• Enabled—This option is enabled.

• Disbled—This option is disabled.

• Auto—The CPU automatically uses default settings.

Enhanced CPU Performance

Enhances CPU performance by adjusting server settings automatically.

4.0(2) and later

Disabled, Auto

• Disabled—This option is Disabled.

• Auto—Allows to adjust server settings to increase the processor performance.

AVX512

The 512-bit extension of the 256-bit Advanced Vector Extensions (AVX) SIMD instructions.

4.3(4b) and later

Auto, Enabled, Disabled

Power Down Enable

Enable or disable the DDR power down mode.

4.3(4b) and later

Auto, Enabled, Disabled

Power Profile Selection F19h

The DF P-state selection in the profile policy is overridden by the P-state range, the BIOS option or the APB_DIS BIOS option.

4.3(4b) and later

High Performance Mode, Efficiency Mode, Maximum IO Performance Mode, Balanced Memory Performance Mode

SEV-ES ASID Space Limit

The SEV-ES and SNP guests must use ASIDs in the range of 1 through 1007.

4.3(4b) and later

xGMI Force Link Width

4.3(4b) and later

Auto, 0, 1, 2

TSME

Provides hardware memory encryption of all the data stored on system DIMMs that is invisible to the OS and slightly increases the memory latency.

4.3(4b) and later

Enabled, Disabled, Auto

4-link xGMI max speed

Specifies the maximum frequency used for XGMI P-state in a 4-link topology.

4.3(4b) and later

20 Gbps, 25 Gbps, 32 Gbps, Auto

Fixed SOC P-State SP5 F19h

Forced P-State to be independent or dependent, as reported by the ACPI _PSD object. It changes the SOC P-State if APBDIS is enabled.

4.3(4b) and later

0 - 2 with 0 as the default.

Fixed SOC P-State

Forced P-State to be independent or dependent, as reported by the ACPI _PSD object. It changes the SOC P-State if APBDIS is enabled.

4.3(4b) and later

Auto, Po, P1, P2,P3

DF PState Frequency Optimizer

Enable or Disable the DF P-state CCLK effective frequency optimizer.

4.3(4b) and later

Auto, Enabled, Disabled

Processor Reserved Memory Range Registers (PRMRR) is the size of the protected region in the system DRAM.

4.3(2) and later

Invalid Config, 1G, 2G, 4G, 8G, 16G, 32G, 64G, 128G, 256G, 512G, 128M, Auto, 256M, 512M

Allows the memory controller to defer the refresh cycles when the memory is active and accomplishes the refresh within a specified window. The deferred refresh cycles may run in a burst of several refresh cycles.

4.0(2) and later

Disabled, Enabled

Allows you to select the Algorithm Performance Boost (APB) Disable value for the SMU.

4.0(2) and later

Auto, 0, 1

• Auto—Sets an auto ApbDis for the SMU. This is the default option.

• 0—Clear ApbDis to SMU

• 1—Set ApbDis to SMU

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.0(2) and later

Auto, TWO (1 + 1), TWO (2 + 0), THREE (3 + 0), FOUR (2 + 2), FOUR (4 + 0)",

"SIX (3 + 3)"

ONE (1 + 0), TWO (2 + 0), THREE (3 + 0), FOUR (4 + 0), FIVE (5 + 0), SIX (6 + 0), SEVEN (7 + 0), EIGHT (8 + 0), NINE (9 + 0), TEN (10 + 0), ELEVEN (11 + 0), TWELVE (12 + 0), THIRTEEN (13 + 0), FOURTEEN (14 + 0), FIFTEEN (15 + 0)

• Auto—The CPU determines how many cores must be enabled. This is the default option.

• ONE (1 + 0)—One core enabled on one CPU complex.

• TWO (2 + 0)—Two cores enabled on one CPU complex.

• THREE (3 + 0)—Three cores enabled on one CPU complex.

• FOUR (4 + 0)—Four cores enabled on one CPU complex.

• FIVE (5 + 0)—Five cores enabled on one CPU complex.

• SIX (6 + 0)—Six cores enabled on one CPU complex.

• SEVEN (7 + 0)—Seven cores enabled on one CPU complex.

• EIGHT (8 + 0)—Eight cores enabled on one CPU complex.

• NINE (9 + 0)—Nine cores enabled on one CPU complex.

• TEN (10 + 0)—Ten cores enabled on one CPU complex.

• ELEVEN (11 + 0)—Eleven cores enabled on one CPU complex.

• TWELVE (12 + 0)—Twelve cores enabled on one CPU complex.

• THIRTEEN (13 + 0)—Thirteen cores enabled on one CPU complex.

• FOURTEEN (14 + 0)—Fourteen cores enabled on one CPU complex.

• FIFTEEN (15 + 0)—Fifteen cores enabled on one CPU complex.

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.0(2) and later

Auto, TWO (1 + 1), TWO (2 + 0), THREE (3 + 0), FOUR (2 + 2), FOUR (4 + 0), SIX (3 + 3)

• Auto—The CPU determines how many cores must be enabled. This is the default option.

• TWO (1 + 1)—One core enabled on one CPU complex.

• TWO (2 + 0)—Two cores enabled on one CPU complex.

• THREE (3 + 0)—Three cores enabled on one CPU complex.

• FOUR (4 + 0)—Four cores enabled on one CPU complex.

• FIVE (5 + 0)—Five cores enabled on one CPU complex.

• SIX (3 + 3)—Six cores enabled on one CPU complex.

CPU Downcore control F19 M10h-1Fh

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.3(4b) and later

Auto, ONE (1 + 0), TWO (2 + 0), THREE (3 + 0), FOUR (4 + 0), FIVE (5 + 0), SIX (6 + 0), SEVEN (7 + 0), EIGHT (8 + 0), NINE (9 + 0), TEN (10 + 0), ELEVEN (11 + 0), TWELVE (12 + 0), THIRTEEN (13 + 0), FOURTEEN (14 + 0), FIFTEEN (15 + 0)

Enables the streaming store functionality.

4.0(2) and later

Auto, Disabled, Enabled

This option defines the target P-state when APBDIS (to disable Algorithm Performance Boost (APB)) is set. The P-x specify a valid P-state for the processor installed.

4.0(2) and later

Auto, P0, P1, P2, P3

• Auto—Sets a valid P-state suitable for the processor. This is the default option.

• P0 to P3—Highest-performing SOC P-state to lowest-performing SOC P-state.

When long duration idleness is expected in a system, this control allows the system to transition into a DF C-state which can set the system into an even lower power state.

4.0(2) and later

Auto, Disabled, Enabled

Allows you to specify the number of charge-coupled device CCDs that are desired to be enable in the system.

4.0(2) and later

Auto, 2 CCDs, 3 CCDs, 4 CCDs, 6 CCDs, 8 CCDs, 10 CCDs

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.0(2) and later

Auto, ONE (1 + 0), TWO (2 + 0), THREE (3 + 0), FOUR (4 + 0), FIVE (5 + 0), SIX (6 + 0), SEVEN (7 + 0)

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.0(2) and later

Auto, TWO (1 + 1),TWO (2 + 0), THREE (3 + 0), FOUR (2 + 2), SIX (3 + 3)

Creates a layer of virtual domains on top of the physical domains in which each Cisco Compatible Extensions is declared to be in its on domain.

4.2(1) and later

Auto, Disabled, Enabled

This option enables 18 Gbps XGMI link speed.

4.0(2)

Disabled, Enabled

Enables or disables the EDC Shutdown Protection which enhances the utilization tracking to avoid EDC shutdown responses to specific aggressive workloads.

4.3(4a) and later

Auto, Enabled, Disabled

This value controls the Dynamic Link Width Management (DLWM) feature.

When the platform can support either an 8 lane or 16 lane xGMI operation, the dynamic adjustment feature provides power savings.

4.3(4a) and later

Auto, Enabled, Disabled

Selects the APIC mode to be used.

4.3(4a) and later

PCIe Ten Bit Tag Support

Enables the PCIe ten bit tags for the supported devices.

4.3(4a) and later

Auto, Enabled, Disabled

Whether the processor uses AMD Simultaneous MultiThreading Technology, which allows multithreaded software applications to execute threads in parallel within each processor.

4.0(2) and later

Disabled, Enabled, Auto, Off

Whether the processor uses AMD Secure Virtual Machine Technology.

4.0(2) and later

Disabled, Enabled

Memory Clock Speed 7xx3 (AMD 3rd Gen CPU)

Allows the memory clock to be further reduced from the maximum platform limit.

4.3(4a) and later

Auto, 800 MHz, 933 MHz, 1067 MHz, 1200 MHz, 1333 MHz, 1467MHz, 1600 MHz, 1633 MHz, 1667MHz, 1700 MHz, 1733 MHz, 1767 MHz, 1800 MHz, 400 MHz

Allows the memory clock to be further reduced from the maximum platform limit.

4.3(4a) and later

Auto, 667 MHz, 800 MHz, 933 MHz, 1067 MHz, 1200 MHz, 1333 MHz, 1467 MHz, 1600 MHz

4.3(4a) and later

Auto, 2 xGMI Links, 3 xGMI Links, 4 xGMI Links

Preferred IO 7xx3(AMD 3rd Gen CPU)

Enables the feature for a preferred bus as a performance improvement.

4.3(4a) and later

Auto, Bus

Preferred IO 7xx2 (AMD 2nd Gen CPU)

Enables the feature for a preferred bus as a performance improvement.

4.3(4a) and later

Auto, Manual

Core Watchdog Timer Enable

Enables or disables CPU watchdog timer.

4.3(4a) and later

Auto, Enabled, Disabled

IIO eDPC Support

The eDPC (Enhanced Downstream Port Containment) allows a downstream link to be disabled after an uncorrectable error, enabling recovery possible in a controlled and robust manner.

4.3(6c) and later

Disabled, On Fatal Error, On Fatal and Non-Fatal Errors

• Disabled—eDPC support is turned off, and the system does not take any action to disable downstream links in response to errors.

• On Fatal Error—eDPC is enabled only for fatal errors.is not supported on Cisco UCS C225 M8, Cisco UCS C245 M8, and X215c M8 servers.

• On Fatal and Non-Fatal Errors—eDPC is enabled for both fatal and non-fatal errors.

What Baud rate is used for the serial port transmission speed. If you disable Console Redirection, this option is not available.

4.2(1) and later

9.6k, 19.2k, 38.4k, 57.6k, 115.2k

Consistent Device Naming allows Ethernet interfaces to be named in a consistent manner. This makes Ethernet interface names more uniform, easy to identify, and persistent when adapter or other configuration changes are made.

4.2(1) and later

Enabled, Disabled

This option denotes the type of messages in BIOS tech log file.

4.2(1) and later

Maximum, Minimum, Normal

• Maximum—Critical messages will be displayed in the log file. This is the default option

• Minimum—Warning and loading messages will be displayed in the log file.

• Normal—Normal and information related messages will be displayed in the log file.

The Option ROM launch is controlled at the PCI Slot level, and is enabled by default. In configurations that consist of a large number of network controllers and storage HBAs having Option ROMs, all the Option ROMs may get launched if the PCI Slot Option ROM Control is enabled for all. However, only a subset of controllers may be used in the boot process. When this token is enabled, Option ROMs are launched only for those controllers that are present in boot policy.

4.2(1) and later

Enabled, Disabled

Allows a serial port to be used for console redirection during POST and BIOS booting. After the BIOS has booted and the operating system is responsible for the server, console redirection is irrelevant and has no effect

4.2(1) and later

Disabled, COM 0, COM 1

• COM 0 enables serial port for console redirection during POST. This option is valid only for M6 blade servers and rack-mount servers.

• COM 1 or serial-port-b enables serial port B for console redirection and allows it to perform server management tasks. This option is only valid for rack-mount servers.

Whether a handshake protocol is used for flow control. Request to Send / Clear to Send (RTS/CTS) helps to reduce frame collisions that can be introduced by a hidden terminal problem.

4.2(1) and later

None, RTC-CTS

Whether the FRB2 timer is used for recovering the system if it hangs during POST.

4.2(1) and later

Enabled, Disabled

Whether the BIOS programs the watchdog timer with a predefined timeout value. If the operating system does not complete booting before the timer expires, the CIMC resets the system and an error is logged.

4.2(1) and later

Enabled, Disabled

What action the system takes if the watchdog timer expires.

4.2(1) and later

Power-off, Reset

What timeout value the BIOS uses to configure the watchdog timer.

4.2(1) and later

5 minutes, 10 minutes, 15 minutes, 20 minutes

Serial Mux

Enables or disables the serial mux configuration.

4.3(4a) and later

Serial Mux

What type of character formatting is used for console redirection.

4.2(1) and later

PC-ANSI, VT100, VT100-PLUS, VT-UTF8

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 1 or SHA-1 PCR Bank allows to enable or disable TPM security.

4.2(1) and later

Enabled, Disabled

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 256-bit or SHA-256PCR Bank allows to enable or disable TPM security.

4.2(1) and later

Enabled, Disabled

SHA384 PCR Bank

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 384-bit or SHA-384PCR Bank allows to enable or disable TPM security.

4.3(3a) and later

Enabled, Disabled

Whether to enable or disable the Trusted Platform Module (TPM), which is a component that securely stores artifacts that are used to authenticate the server.

4.2(1) and later

Enabled, Disabled

Trusted Platform Module (TPM) Pending Operation option allows you to control the status of the pending operation.

4.2(1) and later

None, TpmClear

Security Device Support

It controls the entire TPM functionality.

4.2(3) and later

Enabled, Disabled

Enables or disables IPv4 support for HTTP.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—IPv4 HTTP support is not available.

• Enabled—IPv4 HTTP support is made available.

IPV6 HTTP Support

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—IPv6 HTTP support is not available.

• Enabled—IPv6 HTTP support is made available.

Enables or disables IPv4 support for PXE.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—IPv4 PXE support is not available.

• Enabled—IPv4 PXE support is made available.

Enables or disables IPv6 support for PXE.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—IPv6 PXE support is not available.

• Enabled—IPv6 PXE support is made available.

This option allows you to enable or disable the complete network style of the system.

6.0(1.260001) and later

✔

Disabled,Enabled

• Disabled—Network Stack support is not available.

• Enabled—Network Stack support is available.

Power ON Password

This token requires that you set a BIOS password before using the F2 BIOS configuration. If enabled, password needs to be validated before you access BIOS functions such as IO configuration, BIOS set up, and booting to an operating system using BIOS.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—Power On Password is disabled.

• Enabled—Power On Password is enabled.

PreBoot DMA Protection

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled

  ——Options are Disabled.

• Enabled

  ——Options are Enabled.

CDN Support for LOM

Whether the Ethernet Networking Identifier naming convention is according to Consistent Device Naming (CDN) or the traditional way of naming conventions.

6.0(1.260001) and later

✔

Enabled, Disabled

• Disabled OS Ethernet Networking Identifier is named in a default convention as ETH0, ETH1 and so on.

• Enabled OS Ethernet Network Identifier is named in a consistent device naming (CDN) convention according to the physical LAN on Motherboard (LOM) port numbering; LOM Port 0, LOM Port 1 and so on.

This option allows a downstream link to be disabled after an uncorrectable error, making recovery possible in a controlled and robust manner.

6.0(1.260001) and later

✔

Disabled, On fatal error, On fatal and non-fatal error

Whether the server can use the Option ROMs present in the PCIe MSTOR RAID.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—Option ROM is not available.

• Enabled—Option ROM is available.

Link speed for PCIe Slot designated by slot n.

6.0(1.260001) and later

✔

Disabled, Auto, GEN1, GEN2, GEN3, GEN4, GEN5

GEN5 is supported only for speeds 1 to 6.

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed

• Gen 3—8GT/s is the maximum speed allowed

• Gen 4—16GT/s is the maximum speed allowed

• Gen 5—32 GT/s is the maximum speed allowed

For C245 M8 platform, n ranges from 1 to 4.

This option allows you to restrict the maximum speed of an NVME card installed in the front PCIe slot.

6.0(1.260001) and later

✔

Disabled, Auto, GEN1, GEN2, GEN3, GEN4, GEN5

• Disabled—Maximum speed is not restricted.

• Auto—The maximum speed is set automatically.

• Gen 1—2.5GT/s (gigatransfers per second) is the maximum speed allowed.

• Gen 2—5GT/s is the maximum speed allowed

• Gen 3—8GT/s is the maximum speed allowed

• Gen 4—16GT/s is the maximum speed allowed

• Gen 5—32GT/s is the maximum speed allowed

For C245 M8 platform, n ranges from 1 to 4.

This options allows you to control the Option ROM execution of the PCIe adapter connected to the SSD:NVMe slot n.

6.0(1.260001) and later

✔

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Whether Option ROM is available on the MLOM port.

6.0(1.260001) and later

✔

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

• UEFI only—The expansion slot is available only for UEFI.

• Legacy only—The expansion slot is available only for legacy.

Whether Option ROM is available on the port.

6.0(1.260001) and later

✔

Disabled, Enabled, Legacy only, UEFI only

• Disabled—The expansion slot is not available.

• Enabled—The expansion slot is available.

Re-Size BAR Support

Allows to enable or disable Re-sizable BAR support setup item.

6.0(1.260001) and later

✔

Enabled, Disabled

PCIe Slots CDN Control where, CDN refers to Consistent Device Naming

PCIe Slots Consistent Device Naming (CDN) control allows PCIe slots to be named in a consistent manner. This makes PCIe slot names more uniform, easy to identify, and persistent when the configuration changes are made.

6.0(1.260001) and later

✔

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

PCIe Slots Consistent Device Naming (CDN) control allows PCIe slots to be named in a consistent manner. This makes PCIe slot names more uniform, easy to identify, and persistent when the configuration changes are made.

6.0(1.260001) and later

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

Enables or disables the ACPI SRAT SP Memory flag when the UEFI Memory Map Special Purpose Flag is enabled.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

UEFI Memory Map Special Purpose Memory Flag

Changing the UEFI Memory Map Special knob settings impacts CXL cards on certain operating systems.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

6.0(1.260001) and later

✔

Disabled, Enabled, Auto

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

• Auto—Option is in auto mode.

Allows you to disable the PCI BME bit to mitigate the threat from an unauthorized external DMA

6.0(1.260001) and later

✔

Enabled, Disabled

• Disabled—Option is not restricted.

• Enabled—Option is restricted.

MMIO High Granularity Size

Selects the allocation size that is used to assign memory-mapped I/O (MMIO) resources.

6.0(1.260001) and later

✔

1G, 4G, 16G, 32G, 64G, 256G, 1024G, Auto

MMIO High Base

The base memory size according to memory-address mapping for the I/O (MMIO resources)

6.0(1.260001) and later

✔

512G, 1T, 2T, 4T, 16T, 24T, 32T, 40T, 56T, Auto

Limits the capacity in Partial Memory Mirror Mode up to 50 percent of the total memory capacity. The memory size can range from 0 GB to 65535 GB in increments of 1 GB.

6.0(1.260001) and later

✔

0 - 65535 with a step size of 1

Provides a protective mechanism to ensure the memory temperature is within the limits. When the temperature exceeds the maximum threshold value, the memory access rate is reduced and Baseboard Management Controllerf (BMC) adjusts the fan to cool down the memory to avoid DIMM damage due to overheat

6.0(1.260001) and later

✔

CLTT with PECI, Disabled

• Disabled—Options are Disabled.

• CLTT with PECI—Closed Loop Thermal Throttling (CLTT) with Platform Environment Control Interface (PECI).

Whether the BIOS supports NUMA.

6.0(1.260001) and later

✔

Enabled, Disabled

• Disabled—The BIOS does not support NUMA.

• Enabled—The BIOS includes the ACPI tables that are required for NUMA-aware operating systems. If you enable this option, the system must disable Inter-Socket Memory interleaving on some platforms.

enables you to partially mirror by GB or by a percentage of the memory capacity. Depending on the option selected here, you can define either a partial mirror percentage or a partial mirror capacity in GB in available fields. You can partially mirror up to 50 percent of the memory capacity.

6.0(1.260001) and later

✔

Disabled, Percentage, Value in GB

• Disabled—Options are Disabled.

• Percentage—The amount of memory to be mirrored in the Partial Memory Mode is defined as a percentage of the total memory.

• Value in GB—The amount of memory to be mirrored in the Partial Memory Mode is defined in GB.

  Note	Partial Memory Mirror Mode is mutually exclusive to standard Mirroring Mode. Partial Mirrors 1-4 can be used in any number or configuration, provided they do not exceed the capacity limit set in GB or Percentage in the related options.

Limits the amount of available memory to be mirrored as a percentage of the total memory. This can range from 0.000.01 % to 50.00 % in increments of 0.01 %.

6.0(1.260001) and later

✔

0.00 - 50.00 with a step size of 0.01

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—This option is Disabled.

• Enabled—This option is enabled.

Runtime Post Package Repair

Enables the soft post-package repairs of the corrected memory errors during OS runtime.

6.0(1.260001) and later

✔

Disabled, Enabled

How the memory reliability, availability, and serviceability (RAS) is configured for the server.

6.0(1.260001) and later

✔

Maximum Performance, Mirroring, Lockstep, Mirror Mode 1LM, Partial Mirror Mode 1LM, Sparing, ADDDC Sparing

• Maximum Performance—Optimizes the system performance and disables all the advanced RAS features.

• Mirroring—System reliability is optimized by using half the system memory as backup. This mode is used for UCS M4 and lower blade servers

• Lockstep—If the DIMM pairs in the server have an identical type, size, and organization and are populated across the SMI channels, you can enable lockstep mode to minimize memory access latency and provide better performance. Lockstep is enabled by default for B440 servers.

• Mirror Mode 1LM—Mirror Mode 1LM will set the entire 1LM memory in the system to be mirrored, consequently reducing the memory capacity by half. This mode is used for UCS M5 and M6 blade servers.

• Partial Mirror Mode 1LM—Partial Mirror Mode 1LM will set a part of the 1LM memory in the system to be mirrored, consequently reducing the memory capacity by half. This mode is used for UCS M5 and M6 blade servers.

• Sparing—System reliability is optimized by holding memory in reserve so that it can be used in case other DIMMs fail. This mode provides some memory redundancy, but does not provide as much redundancy as mirroring.

• ADDDC Sparing—System reliability is optimized by holding memory in reserve so that it can be used in case other DIMMs fail. This mode provides some memory redundancy, but does not provide as much redundancy as mirroring.

Post Package Repair (PPR) provides the ability to repair faulty memory cells by replacing them with spare cells.

6.0(1.260001) and later

✔

Disabled, Hard PPR

• Disabled—Options are Disabled.

• Hard PPR—This results in a permanent remapping of damaged storage cells.

As the name implies, UMA based clustering is the suggested clustering mode when the processor is configured as Uniform Memory Access (UMA) node, i.e. SNC is disabled.

6.0(1.260001) and later

✔

Disable-All-2All, Hemisphere-2-clusters, Quadrant-4-clusters

Error Check Scrub

Allows you to enable a memory device to perform memory checking, correction and count errors.

6.0(1.260001) and later

✔

Disabled, Enabled with result collection, Enabled without result collection

Rank Margin Tool

Allows automated memory margin testing and is used to identify DDR margins at the rank level.

6.0(1.260001) and later

✔

Enabled, Disabled

Adaptive Refresh Management Level

Selects Adaptive Refresh Management (ARFM) Level when refresh management (RFM) is required.

6.0(1.260001) and later

✔

Whether to enable or disable memory mapped I/O of 64-bitPCI devices to 4GB or greater address space. Legacy option ROMs are not able to access addresses above 4GB. PCI devices that are 64-bit compliant but use a legacy option ROM may not function correctly with this setting enabled.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This options is enabled.

Enhanced CPU Performance

Enhances CPU performance by adjusting server settings automatically.

6.0(1.260001) and later

✔

Disabled, Auto

• Disabled—This option is Disabled.

• Auto—Allows to adjust server settings to increase the processor performance.

In CPU non-inclusive cache scheme, Mid-Level Cache (MLC) evictions are filled into the Last-Level Cache (LLC). When lines are evicted from the MLC, the core can flag them as dead (not likely to be read again). The LLC has the option to drop dead lines and not fill them in the LLC.

6.0(1.260001) and later

✔

Disabled, Enabled, Auto

• Disabled—The dead lines are always dropped and are never filled into the LLC.

• Enable—Allows the LLC to fill dead lines into the LLC if there is free space available. This is the default option.

• Auto—The CPU determines the LLC dead line allocation.

This feature allows an LLC request to be duplicated and sent to an appropriate memory controller in a remote machine based on the recent LLC history to reduce latency.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This options is enabled.

• Auto—The CPU determines the functionality.

Latency Optimized Mode

A set of BIOS settings that prioritize low latency and consistent performance over energy efficiency or other optimizations.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—Options are Disabled.

• Enabled—Options are enabled.

QPI Link Frequency Select

6.0(1.260001) and later

✔

Auto, 9.6 GT/s, 10.4 GT/s, 11.2GT/s, 12.8GT/s, 14.4GT/s, 16.0GT/s, 20.0GT/s, 16.0GT/s, 20.0GT/s,24.0GT/s, Auto, Use Per Link Setting

Whether the front panel USB devices are enabled or disabled.

6.0(1.260001) and later

✔

Enabled, Disabled

Whether the USB Port KVM devices are enabled or disabled.

6.0(1.260001) and later

✔

Enabled, Disabled

Whether the USB port rear devices are enabled or disabled.

6.0(1.260001) and later

Enabled, Disabled

Whether the SD card drives are enabled or disabled.

6.0(1.260001) and later

✔

Enabled, Disabled

Processor Reserved Memory Range Registers (PRMRR) is the size of the protected region in the system DRAM.

6.0(1.260001) and later

✔

Invalid Config, 1G, 2G, 4G, 8G, 16G, 32G, 64G, 128G, 256G, 512G, 128M, Auto, 256M, 512M

Whether the processor fetches cache lines in even/odd pairs instead of fetching just the required line.

6.0(1.260001) and later

✔

Disabled, Enabled

• Disabled—This option is Disabled.

• Enable—This option is enabled.

Allows the user to select the BIOS performance state that is set before the operating system handoff.

6.0(1.260001) and later

✔

DFX OSB

Controls the Opportunistic Snoop Broadcast (OSB) feature. OSB is used by CHA to broadcast snoops under lightly loaded ring or Intel UPI link condition. It is used to reduce the latency due to the directory lookup.

6.0(1.260001) and later

✔

Auto, Enabled, Disabled

Allows the CPU to trigger interrupts on corrected machine check events. The corrected machine check interrupt (CMCI) allows faster reaction than the traditional polling timer.

6.0(1.260001) and later

✔

Disabled, Enabled

Allows you to set a customized value for Thermal Design Power (TDP).

6.0(1.260001) and later

✔

Normal, Level 1, Level 2

Sets the state of logical processor cores per CPU in a package. If you choose All as the value, Intel Hyper Threading technology is also enabled.

6.0(1.260001) and later

✔

All, 1 through 86

• All— Enables multiprocessing on all logical processor cores.

• 1 through 86—Specifies the number of logical processor cores per CPU that can run on the server. To disable multiprocessing and have only one logical processor core per CPU running on the server, choose 1.

  Note	For M6 servers, it ranges from 1 through 48.

  Note	1, 2, and 3 options are not applicable for M8 servers.

  Note	From 65 to 86 is applicable for M8 servers only.

Allows you to determine whether system performance or energy efficiency is more important on this server.

6.0(1.260001) and later

✔

Performance, Balanced Performance, Balanced power, power

When energy efficient turbo is enabled, the optimal turbo frequency of the CPU turns dynamic based on CPU utilization. The power/performance bias setting also influences the energy efficient turbo.

6.0(1.260001) and later

✔

Disabled, Enabled

Whether the processor uses Enhanced Intel SpeedStep Technology, which allows the system to dynamically adjust processor voltage and core frequency. This technology can result in decreased average power consumption and decreased average heat production.

6.0(1.260001) and later

✔

Disabled, Enabled

Allows you to determine whether system performance or energy efficiency is more important on this server.

6.0(1.260001) and later

✔

IOAT Configuration

Enables or disables the CPM (Content Processing Module) in IOAT (Intel® I/O Acceleration Technology) accelerators.

6.0(1.260001) and later

✔

Disabled, Enabled

Whether the processor allows the Intel hardware prefetcher to fetch streams of data and instructions from memory into the unified second-level cache when necessary.

6.0(1.260001) and later

✔

Disabled, Enabled

Enables processor Hardware Power Management (HWPM).

6.0(1.260001) and later

✔

Disabled, HWPM Native Mode, HWPM OOB Mode, Native Mode with no Legacy

Intel Dynamic Speed Select modes allow you to run the CPU with different speeds and cores in auto mode.

6.0(1.260001) and later

✔

Disabled, Enabled

Whether the processor uses Intel Hyper-Threading Technology, which allows multithreaded software applications to execute threads in parallel within each processor.

6.0(1.260001) and later

✔

Disabled, Enabled

Whether the processor uses Intel Turbo Boost Technology, which allows the processor to automatically increase its frequency if it is running below power, temperature, or voltage specifications.

6.0(1.260001) and later

✔

Disabled, Enabled

Whether the processor uses Intel Virtualization Technology for Directed I/O (VT-R)

6.0(1.260001) and later

✔

Disabled, Enabled

Whether the processor uses the DCU IP Prefetch mechanism to analyze historical cache access patterns and preload the most relevant lines in the L1 cache.

6.0(1.260001) and later

✔

Disabled, Enabled

KTI prefetch is a mechanism to get the memory read started early on a DDR bus.

6.0(1.260001) and later

✔

Disabled, Enabled, Auto

Whether the processor uses the LLC Prefetch mechanism to fetch the date into the LLC.

4.0(2) and later

✔

Disabled, Enabled

The amount of power available to the server components when they are idle.

6.0(1.260001) and later

✔

No Limit, Auto, C0 C1 State, C2, C6 Non Retention, C6 Retention

It sets the interval for a full memory scan.

6.0(1.260001) and later

✔

Disabled, Enabled

• Enable—The system periodically reads and writes memory searching for ECC errors. If any errors are found, the system attempts to fix them. This option may correct single bit errors before they become multi-bit errors, but it may adversely affect performance when the patrol scrub is running.

• Disable—The system checks for memory ECC errors only when the CPU reads or writes a memory address.

Allows the processor to transition to its minimum frequency upon entering C1. This setting does not take effect until after you have rebooted the server.

6.0(1.260001) and later

✔

Disabled, Enabled

Whether the processor sends the C6 report to the operating system.

6.0(1.260001) and later

✔

Disabled, Enabled

Allows you to define how BIOS communicates the P-state support model to the operating system. There are 3 models as defined by the Advanced Configuration and Power Interface (ACPI) specification.

6.0(1.260001) and later

✔

SW All, HW All, SW Any

Whether the CPU supports sub NUMA clustering, in which the tag directory and the memory channel are always in the same region.

6.0(1.260001) and later

✔

Disabled, Enabled, Auto, SNC2, SNC4

Whether the processor uses the DCU IP Prefetch mechanism to analyze historical cache access patterns and preload the most relevant lines in the L1 cache.

6.0(1.260001) and later

✔

Disabled, Enabled, Auto

Allows you to configure the scaling of the uncore frequency of the processor.

6.0(1.260001) and later

✔

Disabled, Enabled, Mode 0, and Mode 1

Uncore Frequency Scaling IO

Adjusts the frequency of processor uncore components responsible for I/O operations to optimize power and performance.

6.0(1.260001) and later

✔

Mode 1, Mode 0

This feature allows for workload optimization.

6.0(1.260001) and later

✔

Balanced, IO Sensitive

Whether XPT prefetch is used to enable a read request that is sent to the last level cache to issue a copy of that request to the memory controller prefetcher.

6.0(1.260001) and later

✔

Auto, Disabled, Enabled

Intel Speed Select

Allows you to adjust different cores to operate in different frequencies to have a better power efficiency.

The values Config 1 and Config 2 are not supported on Cisco UCS M6 and M7 servers.

For Cisco UCS M6 and Cisco UCS M7 servers, the values Config 3 and Config 4 (4th Gen Intel Xeon Scalable processors and 5th Gen Intel Xeon Scalable processors) are equivalent to the values Config 1 and Config 2 (3rd Gen Intel Xeon Scalable processors).

6.0(1.260001) and later

✔

Auto, Base, Config 1, Config 2, Config 3, Config 4

• Config 1 and Config 2 are options available for M5 servers only with Base as the default.

• Auto is the default for M8.

IIO eDPC Support

The eDPC (Enhanced Downstream Port Containment) allows a downstream link to be disabled after an uncorrectable error, enabling recovery possible in a controlled and robust manner. This can be one of the following:

6.0(1.260001) and later

✔

Disabled, On Fatal Error, On Fatal and Non-Fatal Errors

• Disabled—eDPC support is turned off, and the system does not take any action to disable downstream links in response to errors.

• On Fatal Error—eDPC is enabled only for fatal errors.is not supported on Cisco UCS C225 M8, Cisco UCS C245 M8, and X215c M8 servers.

• On Fatal and Non-Fatal Errors—eDPC is enabled for both fatal and non-fatal errors.

What Baud rate is used for the serial port transmission speed. If you disable Console Redirection, this option is not available.

6.0(1.260001) and later

✔

9.6k, 19.2k, 38.4k, 57.6k, 115.2k

Consistent Device Naming allows Ethernet interfaces to be named in a consistent manner. This makes Ethernet interface names more uniform, easy to identify, and persistent when adapter or other configuration changes are made.

6.0(1.260001) and later

✔

Enabled, Disabled

When this token is enabled, the BIOS saves the memory training results (optimized timing/voltage values) along with CPU/memory configuration information and reuses them on subsequent reboots to save boot time. The saved memory training results are used only if the reboot happens within 24 hours of the last save operation.

6.0(1.260001) and later

✔

Enabled, Disabled

This option denotes the type of messages in BIOS tech log file.

6.0(1.260001) and later

✔

Maximum, Minimum, Normal

• Maximum—Critical messages will be displayed in the log file. This is the default option

• Minimum—Warning and loading messages will be displayed in the log file.

• Normal—Normal and information related messages will be displayed in the log file.

The Option ROM launch is controlled at the PCI Slot level, and is enabled by default. In configurations that consist of a large number of network controllers and storage HBAs having Option ROMs, all the Option ROMs may get launched if the PCI Slot Option ROM Control is enabled for all. However, only a subset of controllers may be used in the boot process. When this token is enabled, Option ROMs are launched only for those controllers that are present in boot policy.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows a serial port to be used for console redirection during POST and BIOS booting. After the BIOS has booted and the operating system is responsible for the server, console redirection is irrelevant and has no effect

6.0(1.260001) and later

✔

Disabled, COM 0, COM 1

• COM 0 enables serial port for console redirection during POST. This option is valid only for M6 blade servers and rack-mount servers.

• COM 1 or serial-port-b enables serial port B for console redirection and allows it to perform server management tasks. This option is only valid for rack-mount servers.

Whether a handshake protocol is used for flow control. Request to Send / Clear to Send (RTS/CTS) helps to reduce frame collisions that can be introduced by a hidden terminal problem.

6.0(1.260001) and later

✔

None, RTC-CTS

Whether the FRB2 timer is used for recovering the system if it hangs during POST.

6.0(1.260001) and later

✔

Enabled, Disabled

Whether the BIOS programs the watchdog timer with a predefined timeout value. If the operating system does not complete booting before the timer expires, the CIMC resets the system and an error is logged.

6.0(1.260001) and later

✔

Enabled, Disabled

What action the system takes if the watchdog timer expires.

6.0(1.260001) and later

✔

Power-off, Reset

What timeout value the BIOS uses to configure the watchdog timer.

6.0(1.260001) and later

✔

5 minutes, 10 minutes, 15 minutes, 20 minutes

What type of character formatting is used for console redirection.

6.0(1.260001) and later

✔

PC-ANSI, VT100, VT100-PLUS, VT-UTF8

MK-TME allows you to have multiple encryption domains with one with own key. Different memory pages can be encrypted with different keys.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows you to enable Software Guard Extensions(SGX) feature.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows you to provide the capability to encrypt the entirety of the physical memory of a system.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows you to change the seed for the security key used for the locked memory region that is created.

6.0(1.260001) and later

✔

SGX Owner EPOCH activated, Change to New Random Owner EPOCHs, Manual User Defined Owner EPOCHs, SGX Owner EPOCH deactivated

Allows you to enable the registration authority service to store the platform keys.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows you to define the SGX EPOCH owner value for the EPOCH number designated by 0.

6.0(1.260001) and later

✔

0 - ffffffffffffffff with a step size of 1

Allows you to define the SGX EPOCH owner value for the EPOCH number designated by 1.

6.0(1.260001) and later

✔

0 - ffffffffffffffff with a step size of 1

Allows the system to perform SGX factory reset on subsequent boot.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows you to set the Software Guard Extensions (SGX) value.

6.0(1.260001) and later

✔

SGX PUBKEY HASH0, SGX PUBKEY HASH1, SGX PUBKEY HASH2, SGX PUBKEY HASH3

• SGX PUBKEY HASH0—Between 7-0.

• SGX PUBKEY HASH1—Between 15-8.

• SGX PUBKEY HASH2—Between 23-16.

• SGX PUBKEY HASH3—Between 31-24.

Allows you to enable SGX Write feature.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows you to enable SGX Package Info In-Band Access.

6.0(1.260001) and later

✔

Enabled, Disabled

Allows you to enable SGX QoS.

6.0(1.260001) and later

✔

Enabled, Disabled

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 1 or SHA-1 PCR Bank allows to enable or disable TPM security.

6.0(1.260001) and later

✔

Enabled, Disabled

The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 256-bit or SHA-256PCR Bank allows to enable or disable TPM security.

6.0(1.260001) and later

✔

Enabled, Disabled

SHA384 PCR Bank