Processor

Processor

The following table lists the Processor BIOS settings that you can configure through a BIOS policy or the default BIOS settings:

Name

Description

Supported Attributes

Versions

Platforms

Values

Dependencies

AVX512

The 512-bit extension of the 256-bit Advanced Vector Extensions (AVX) SIMD instructions.

4.3(4b) and later

C225 M8, C245 M8, X215c M8

Auto, Enabled, Disabled

Power Down Enable

Enable or disable the DDR power down mode.

4.3(4b) and later

C225 M8, C245 M8, X215c M8

Auto, Enabled, Disabled

Power Profile Selection F19h

The DF P-state selection in the profile policy is overridden by the P-state range, the BIOS option or the APB_DIS BIOS option.

where, F refers to the processor family and M denotes the model.

Note

 

F19 tokens are expanding support to include F1A family processors.

4.3(4b) and later

C245 M8, C225 M8, X215c M8

High Performance Mode, Efficiency Mode, Maximum IO Performance Mode, Balanced Memory Performance Mode

SEV-ES ASID Space Limit

The SEV-ES and SNP guests must use ASIDs in the range of 1 through 1007.

4.3(4b) and later

C245 M8, C225 M8, X215c M8

 1-1007, with 1 as the default

xGMI Force Link Width

 The force xGMI link width.

4.3(4b) and later

C245 M8, C225 M8, X215c M8

Auto, 0, 1, 2

TSME

Provides hardware memory encryption of all the data stored on system DIMMs that is invisible to the OS and slightly increases the memory latency.

4.3(4b) and later

C125 M5, C225 M6, C245 M6, C225 M8, C245 M8, X215c M8

Enabled, Disabled, Auto

4-link xGMI max speed

Specifies the maximum frequency used for XGMI P-state in a 4-link topology.

4.3(4b) and later

C245 M8, C225 M8, X215c M8

20 Gbps, 25 Gbps, 32 Gbps, Auto

Fixed SOC P-State SP5 F19h

Forced P-State to be independent or dependent, as reported by the ACPI _PSD object. It changes the SOC P-State if APBDIS is enabled.

where, F refers to the processor family.

Note

 

F19 tokens are expanding support to include F1A family processors.

4.3(4b) and later

C245 M8, C225 M8, X215c M8

0 - 2 with 0 as the default.

Fixed SOC P-State

Forced P-State to be independent or dependent, as reported by the ACPI _PSD object. It changes the SOC P-State if APBDIS is enabled.

4.3(4b) and later

C225 M6, C245 M6

Po, P1, P2,P3

DF PState Frequency Optimizer

Enable or Disable the DF P-state CCLK effective frequency optimizer.

4.3(4b) and later

C245 M8, C225 M8, X215c M8

Auto, Enabled, Disabled

PRMRR Size

Processor Reserved Memory Range Registers (PRMRR) is the size of the protected region in the system DRAM.

4.3(2) and later

B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 , C220 M8, C240 M8, X210c M8, X410c M8, C225 M8, C245 M8, X215c M8, XE1X0M8

Invalid Config, 1G, 2G, 4G, 8G, 16G, 32G, 64G, 128G, 256G, 512G, 128M, Auto, 256M, 512M

Note

 

128M, Auto, 256M, 512M options are available only for M7 servers.
Adjacent Cache Line Prefetcher

Whether the processor fetches cache lines in even/odd pairs instead of fetching just the required line.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled

  • Disabled—This option is Disabled.

  • Enable—This option is enabled.

CPU Performance must be set to Custom to specify this value. For any value other than Custom, this option is overridden by the setting in the selected CPU performance profile.

Autonomous Core C State

Enables CPU Autonomous C-State, which converts the HALT instructions to the MWAIT instructions.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7

Disabled, Enabled

Note

 

This is not applicable to XE1X0M8.
Boot Performance Mode

Allows the user to select the BIOS performance state that is set before the operating system handoff.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 , C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Max Performance, Max Efficient, Set by Intel NM

Note

 

Set by Intel NM option is not applicable for M8 intel platforms.
Burst and Postponed Refresh

Allows the memory controller to defer the refresh cycles when the memory is active and accomplishes the refresh within a specified window. The deferred refresh cycles may run in a burst of several refresh cycles.

4.0(2) and later

C225 M6, C245 M6, C225 M8, C245 M8, X215c M8

Disabled, Enabled

We recommend you to leave this setting in the default state of Disabled to mitigate Rowhammer-style attacks.

APBDIS

Allows you to select the Algorithm Performance Boost (APB) Disable value for the SMU.

4.0(2) and later

C225 M6, C245 M6,C225 M8, C245 M8, X215c M8

Auto, 0, 1

  • Auto—Sets an auto ApbDis for the SMU. This is the default option.

  • 0—Clear ApbDis to SMU

  • 1—Set ApbDis to SMU

DFX OSB

Controls the Opportunistic Snoop Broadcast (OSB) feature. OSB is used by CHA to broadcast snoops under lightly loaded ring or Intel UPI link condition. It is used to reduce the latency due to the directory lookup.

4.3(4a) and later

X410c M7, X210c M7, X210c M8, X410c M8, XE1X0M8

Auto, Enabled, Disabled

Downcore control F19 MA0h-AFh

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

Note

 

This is applicable only for AMD processors of family 19h and for models A0h-AFh. where, F refers to the processor family and M denotes the model

4.0(2) and later

C225 M8, C245 M8, X215c M8

Auto, TWO (1 + 1), TWO (2 + 0), THREE (3 + 0), FOUR (2 + 2), FOUR (4 + 0)",

"SIX (3 + 3)"

ONE (1 + 0), TWO (2 + 0), THREE (3 + 0), FOUR (4 + 0), FIVE (5 + 0), SIX (6 + 0), SEVEN (7 + 0), EIGHT (8 + 0), NINE (9 + 0), TEN (10 + 0), ELEVEN (11 + 0), TWELVE (12 + 0), THIRTEEN (13 + 0), FOURTEEN (14 + 0), FIFTEEN (15 + 0)

  • Auto—The CPU determines how many cores must be enabled. This is the default option.

  • ONE (1 + 0)—One core enabled on one CPU complex.

  • TWO (2 + 0)—Two cores enabled on one CPU complex.

  • THREE (3 + 0)—Three cores enabled on one CPU complex.

  • FOUR (4 + 0)—Four cores enabled on one CPU complex.

  • FIVE (5 + 0)—Five cores enabled on one CPU complex.

  • SIX (6 + 0)—Six cores enabled on one CPU complex.

  • SEVEN (7 + 0)—Seven cores enabled on one CPU complex.

  • EIGHT (8 + 0)—Eight cores enabled on one CPU complex.

  • NINE (9 + 0)—Nine cores enabled on one CPU complex.

  • TEN (10 + 0)—Ten cores enabled on one CPU complex.

  • ELEVEN (11 + 0)—Eleven cores enabled on one CPU complex.

  • TWELVE (12 + 0)—Twelve cores enabled on one CPU complex.

  • THIRTEEN (13 + 0)—Thirteen cores enabled on one CPU complex.

  • FOURTEEN (14 + 0)—Fourteen cores enabled on one CPU complex.

  • FIFTEEN (15 + 0)—Fifteen cores enabled on one CPU complex.

This token is applicable only for the servers with 7xx2 and 7xx3 Model processors.
Downcore control

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.0(2) and later

C125 M5, C225 M6, C245 M6

Auto, TWO (1 + 1), TWO (2 + 0), THREE (3 + 0), FOUR (2 + 2), FOUR (4 + 0), SIX (3 + 3)

  • Auto—The CPU determines how many cores must be enabled. This is the default option.

  • TWO (1 + 1)—One core enabled on one CPU complex.

  • TWO (2 + 0)—Two cores enabled on one CPU complex.

  • THREE (3 + 0)—Three cores enabled on one CPU complex.

  • FOUR (4 + 0)—Four cores enabled on one CPU complex.

  • FIVE (5 + 0)—Five cores enabled on one CPU complex.

  • SIX (3 + 3)—Six cores enabled on one CPU complex.

CPU Downcore control F19 M10h-1Fh

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

Note

 

This is applicable only for AMD processors of family 19h and for models 10h-1Fh. where, F refers to the processor family and M denotes the model

Note

 

F19 tokens are expanding support to include F1A family processors.

4.3(4b) and later

C245 M8, C225 M8, X215c M8

Auto, ONE (1 + 0), TWO (2 + 0), THREE (3 + 0), FOUR (4 + 0), FIVE (5 + 0), SIX (6 + 0), SEVEN (7 + 0), EIGHT (8 + 0), NINE (9 + 0), TEN (10 + 0), ELEVEN (11 + 0), TWELVE (12 + 0), THIRTEEN (13 + 0), FOURTEEN (14 + 0), FIFTEEN (15 + 0)

Streaming Stores Control

Enables the streaming store functionality.

4.0(2) and later

C225 M6, C245 M6, C245 M8, C225 M8, X215c M8

Auto, Disabled, Enabled

Fixed SOC P-State

This option defines the target P-state when APBDIS (to disable Algorithm Performance Boost (APB)) is set. The P-x specify a valid P-state for the processor installed.

4.0(2) and later

C225 M6, C245 M6, C245 M8, C225 M8, X215c M8

Auto, P0, P1, P2, P3

  • Auto—Sets a valid P-state suitable for the processor. This is the default option.

  • P0 to P3—Highest-performing SOC P-state to lowest-performing SOC P-state.

DF C-States

When long duration idleness is expected in a system, this control allows the system to transition into a DF C-state which can set the system into an even lower power state.

4.0(2) and later

C225 M6, C245 M6, C245 M8, C225 M8, X215c M8

Auto, Disabled, Enabled

CCD Control

Allows you to specify the number of charge-coupled device CCDs that are desired to be enable in the system.

4.0(2) and later

C225 M6, C245 M6,C245 M8, C225 M8, X215c M8

Auto, 2 CCDs, 3 CCDs, 4 CCDs, 6 CCDs, 8 CCDs, 10 CCDs

Note

 

  • 2 CCDs, 3 CCDs, 4 CCDs, 6 CCDs options are available only for M6 servers.

  • 2 CCDs, 4 CCDs, 6 CCDs, 8 CCDs, and 10 CCDs options are available only for M8 servers.
CPU Downcore control 7xx3chk m5 and m6 and update

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.0(2) and later

C225 M6, C245 M6

Auto, ONE (1 + 0), TWO (2 + 0), THREE (3 + 0), FOUR (4 + 0), FIVE (5 + 0), SIX (6 + 0), SEVEN (7 + 0)

Downcore control

Provides the ability to remove one or more cores from operation is supported in the silicon. It may be desirable to reduce the number of cores due to operating system restrictions, or power reduction requirements of the system. This item allows the control on the number of cores that are running. This setting can only reduce the number of cores from only those available in the processor.

4.0(2) and later

C125 M5

Auto, TWO (1 + 1),TWO (2 + 0), THREE (3 + 0), FOUR (2 + 2), SIX (3 + 3)

ACPI SRAT L3 Cache As NUMA Domain

Creates a layer of virtual domains on top of the physical domains in which each Cisco Compatible Extensions is declared to be in its on domain.

4.2(1) and later

C225 M6, C245 M6,C245 M8, C225 M8, X215c M8

Auto, Disabled, Enabled

Cisco xGMI Max Speed

This option enables 18 Gbps XGMI link speed.

4.0(2)

C225 M6, C245 M6

Disabled, Enabled

Processor CMCI

Allows the CPU to trigger interrupts on corrected machine check events. The corrected machine check interrupt (CMCI) allows faster reaction than the traditional polling timer.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, X210c M7, C220 M6, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
Configurable TDP Level

Allows you to set a customized value for Thermal Design Power (TDP).

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Normal, Level 1, Level 2

Core Multi Processing

Sets the state of logical processor cores per CPU in a package. If you choose All as the value, Intel Hyper Threading technology is also enabled.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

All, 1 through 86

  • All— Enables multiprocessing on all logical processor cores.

  • 1 through 86—Specifies the number of logical processor cores per CPU that can run on the server. To disable multiprocessing and have only one logical processor core per CPU running on the server, choose 1.

Note

 

1, 2, and 3 options are not applicable for M8 servers.

Note

 

From 65 to 86 is applicable for M8 servers only.

Note

 

From 1 to 64 is applicable for M7 servers only.

Note

 

From 1 to 42 is applicable for XE1X0M8 server only.

We recommend that you contact your operating system vendor to make sure your operating system supports this feature.
Energy Performance

Allows you to determine whether system performance or energy efficiency is more important on this server.

4.0(2) and later

B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Performance, Balanced Performance, Balanced power, power

Power Technology must be set to Custom or the server ignores the setting for this parameter.

CPU Performance

CPU performance by adjusting server settings automatically.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, XE1X0M8

Disabled, Enabled

EDC Control Throttle

Enables or disables the EDC Shutdown Protection which enhances the utilization tracking to avoid EDC shutdown responses to specific aggressive workloads.

4.3(4a) and later

 C245 M6, C225 M6

Auto, Enabled, Disabled

DLWM Support

This value controls the Dynamic Link Width Management (DLWM) feature.

When the platform can support either an 8 lane or 16 lane xGMI operation, the dynamic adjustment feature provides power savings.

4.3(4a) and later

 C245 M6, C225 M6

Auto, Enabled, Disabled

Energy Efficient Turbo

When energy efficient turbo is enabled, the optimal turbo frequency of the CPU turns dynamic based on CPU utilization. The power/performance bias setting also influences the energy efficient turbo.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled

Enhanced Intel Speedstep(R) Technology

Whether the processor uses Enhanced Intel SpeedStep Technology, which allows the system to dynamically adjust processor voltage and core frequency. This technology can result in decreased average power consumption and decreased average heat production.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
Processor EPP Enable

Allows you to determine whether system performance or energy efficiency is more important on this server.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5

Disabled, Enabled
Processor EPP Profile

Allows you to determine whether system performance or energy efficiency is more important on this server.

4.0(2) and later

C220 M6, C240 M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Performance, Balanced Performance, Balanced power, power
Execute Disable Bit

Classifies memory areas on the server to specify where the application code can execute. As a result of this classification, the processor disables code execution if a malicious worm attempts to insert code in the buffer. This setting helps to prevent damage, worm propagation, and certain classes of malicious buffer overflow attacks.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5

Disabled, Enabled

IOAT Configuration

Enables or disables the CPM (Content Processing Module) in IOAT (Intel® I/O Acceleration Technology) accelerators.

4.3(3c) and later

C220 M7, C240 M7, X210 M7, X410 M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
Local APIC Mode*

Selects the APIC mode to be used.

4.3(4a) and later

C245 M6, C225 M6, C225 M8, C245 M8, X215c M8

 Compatibility, XAPIC, X2APIC, Auto
Local X2 Apic

Allows you to set the type of Advanced Processor Interrupt controller (APIC) architecture.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7

Disabled, Enabled

Hardware Prefetcher

Whether the processor allows the Intel hardware prefetcher to fetch streams of data and instructions from memory into the unified second-level cache when necessary.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
CPU Hardware Power Management

Enables processor Hardware Power Management (HWPM).

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, XE1X0M8

Disabled, HWPM Native Mode, HWPM OOB Mode, Native Mode with no Legacy

IMC Interleaving

This BIOS option controls the interleaving between the Integrated Memory Controllers (IMCs).

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5

Auto, 1-way Interleave, 2-way Interleave

Intel Dynamic Speed Select

Intel Dynamic Speed Select modes allow you to run the CPU with different speeds and cores in auto mode.

4.0(2) and later

B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled

Intel HyperThreading Tech

Whether the processor uses Intel Hyper-Threading Technology, which allows multithreaded software applications to execute threads in parallel within each processor.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
Intel Turbo Boost Tech

Whether the processor uses Intel Turbo Boost Technology, which allows the processor to automatically increase its frequency if it is running below power, temperature, or voltage specifications.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled

Intel(R) VT

Whether the processor uses Intel Virtualization Technology for Directed I/O (VT-R)

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
DCU IP Prefetcher

Whether the processor uses the DCU IP Prefetch mechanism to analyze historical cache access patterns and preload the most relevant lines in the L1 cache.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
KTI Prefetch

KTI prefetch is a mechanism to get the memory read started early on a DDR bus.

4.0(2) and later

B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled, Auto

Note

 

Auto option is not applicable for M5 servers.
LLC Prefetch

Whether the processor uses the LLC Prefetch mechanism to fetch the date into the LLC.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled
Package C State Limit

The amount of power available to the server components when they are idle.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

No Limit, Auto, C0 C1 State, C2, C6 Non Retention, C6 Retention

Note

 

C6 Retention option is not applicable for M8 servers.

If you are changing the Package C State Limit token then ensure that the Power Technology is set to Custom.

Patrol Scrub

It sets the interval for a full memory scan.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled

  • Enable—The system periodically reads and writes memory searching for ECC errors. If any errors are found, the system attempts to fix them. This option may correct single bit errors before they become multi-bit errors, but it may adversely affect performance when the patrol scrub is running.

  • Disable—The system checks for memory ECC errors only when the CPU reads or writes a memory address.

The lower the interval, the more memory bandwidth is used for scrubbing.
Patrol Scrub Configuration

It sets the interval for a full memory scan.

4.0(2) and later

B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7

Enabled, Disabled, Enable at End of POST

  • Enable—The system periodically reads and writes memory searching for ECC errors. If any errors are found, the system attempts to fix them. This option may correct single bit errors before they become multi-bit errors, but it may adversely affect performance when the patrol scrub is running.

  • Disable—The system checks for memory ECC errors only when the CPU reads or writes a memory address.

Note

 

Enabled option is applicable for M6 servers only.
Processor C1E

Allows the processor to transition to its minimum frequency upon entering C1. This setting does not take effect until after you have rebooted the server.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled

Note

 

It is Enabled by default for XE1X0M8.
Processor C6 Report

Whether the processor sends the C6 report to the operating system.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled

PCIe Ten Bit Tag Support

Enables the PCIe ten bit tags for the supported devices.

4.3(4a) and later

 C225 M6, C245 M6, C225 M8, C245 M8, X215c M8

Auto, Enabled, Disabled

P STATE Coordination

Note

 

It is also called EIST PSD Function in UCSM.

Allows you to define how BIOS communicates the P-state support model to the operating system. There are 3 models as defined by the Advanced Configuration and Power Interface (ACPI) specification.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

SW All, HW All, SW Any

Note

 

SW Any option is available for M5 servers only.

Power Technology must be set to Custom or the server ignores the setting for this parameter.

Power Performance Tuning

Determines if the BIOS or Operating System can turn on the energy performance bias tuning. The options are BIOS and operating system.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7,C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

BIOS, OS, PECI

Note

 

PECI option is available for M6 and M7 servers only.
UPI Link Frequency Select

Allows you to select different UPI link frequency running.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8

Auto, 9.6GT/S, 10.4GT/S, 11.2GT/S, 12.8GT/s, 14.4GT/s, 16.0GT/s, 20.0GT/s, 24.0GT/s, Use Per Link Setting

Note

 

  • 12.8GT/s, 14.4GT/s, 16.0GT/s, 20.0GT/s options are available for M7 servers only.

  • 11.2GT/S option is available for M6 server only.

  • 16,20, 24, Auto, Use Per Link Setting is applicable for M8 servers only

Note

 

Not applicable for XE1X0M8.
SMT Mode

Whether the processor uses AMD Simultaneous MultiThreading Technology, which allows multithreaded software applications to execute threads in parallel within each processor.

4.0(2) and later

C125 M5, C225 M6, C245 M6, C225 M8, C245 M8, X215c M8

Disabled, Enabled, Auto, Off

Note

 

Off options are available for M5 servers only with Auto as the default.

Sub Numa Clustering

Whether the CPU supports sub NUMA clustering, in which the tag directory and the memory channel are always in the same region.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled, Auto, SNC2, SNC4

Note

 

  • Auto option is available for M5, M7, and M8 servers only.

  • Enabled option is available for M6 and M8 servers only.

  • Disabled option is available for M6, M7, and M8 servers only.

  • SNC2, SNC4 options are available for M7 and M8 servers only.
DCU Streamer Prefetch

Whether the processor uses the DCU IP Prefetch mechanism to analyze historical cache access patterns and preload the most relevant lines in the L1 cache.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled, Auto

Note

 

Auto option is applicable to M8 intel platforms only.
SVM Mode

Whether the processor uses AMD Secure Virtual Machine Technology.

4.0(2) and later

C215 M5, C225 M6, C245 M6, C225 M8, C245 M8, X215c M8

Disabled, Enabled
Uncore Frequency Scaling

Allows you to configure the scaling of the uncore frequency of the processor.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Disabled, Enabled, Mode 0, and Mode 1

Note

 

Mode 0 and Mode 1 is applicable for M8 servers only with Mode 1 being default.

Mode 1 is the default for XE1X0M8.

Uncore Frequency Scaling IO

Adjusts the frequency of processor uncore components responsible for I/O operations to optimize power and performance.

6.0(1a.0) and later

C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Mode 1, Mode 0

Workload Configuration

This feature allows for workload optimization.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Balanced, IO Sensitive
XPT Prefetch

Whether XPT prefetch is used to enable a read request that is sent to the last level cache to issue a copy of that request to the memory controller prefetcher.

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 , C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Auto, Disabled, Enabled

X2APIC Opt-Out Flag

Prevents the operating system from enabling extended xAPIC (x2APIC) mode when the OS is not working with x2APIC.

4.2(3) and later

C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7

Disabled, Enabled

Intel Speed Select

Allows you to adjust different cores to operate in different frequencies to have a better power efficiency.

The values Config 1 and Config 2 are not supported on Cisco UCS M6 and M7 servers.

For Cisco UCS M6 and Cisco UCS M7 servers, the values Config 3 and Config 4 (4th Gen Intel Xeon Scalable processors and 5th Gen Intel Xeon Scalable processors) are equivalent to the values Config 1 and Config 2 (3rd Gen Intel Xeon Scalable processors).

4.0(2) and later

B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7 , C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Auto, Base, Config 1, Config 2, Config 3, Config 4

  • Config 1 and Config 2 are options available for M5 servers only with Base as the default.

  • Auto is the default for M8.

Memory Clock Speed 7xx3 (AMD 3rd Gen CPU)

Allows the memory clock to be further reduced from the maximum platform limit.

4.3(4a) and later

C245 M6, C225 M6

Auto, 800 MHz, 933 MHz, 1067 MHz, 1200 MHz, 1333 MHz, 1467MHz, 1600 MHz, 1633 MHz, 1667MHz, 1700 MHz, 1733 MHz, 1767 MHz, 1800 MHz, 400 MHz

Memory Clock Speed 7xx2 (AMD 2nd Gen CPU)

Allows the memory clock to be further reduced from the maximum platform limit.

4.3(4a) and later

C245 M6, C225 M6

Auto, 667 MHz, 800 MHz, 933 MHz, 1067 MHz, 1200 MHz, 1333 MHz, 1467 MHz, 1600 MHz

xGMI Link Configuration Configures the number of xGMI2 links used on a multi-socket system.

4.3(4a) and later

C245 M6, C225 M6

Auto, 2 xGMI Links, 3 xGMI Links, 4 xGMI Links

Note

 

2 xGMI Links is not supported for C245 M6, C225 M6 platforms.

Preferred IO 7xx3(AMD 3rd Gen CPU)

Enables the feature for a preferred bus as a performance improvement.

4.3(4a) and later

C245 M6, C225 M6

Auto, Bus

Preferred IO 7xx2 (AMD 2nd Gen CPU)

Enables the feature for a preferred bus as a performance improvement.

4.3(4a) and later

C245 M6, C225 M6

Auto, Manual

Core Watchdog Timer Enable

Enables or disables CPU watchdog timer.

4.3(4a) and later

C245 M6, C225 M6

Auto, Enabled, Disabled

IIO eDPC Support

The eDPC (Enhanced Downstream Port Containment) allows a downstream link to be disabled after an uncorrectable error, enabling recovery possible in a controlled and robust manner. This can be one of the following:

4.3(6c) and later

C220 M8, C240 M8, C225 M8, C245 M8, X215c M8, C220 M7, C240 M7, C220 M6, C240 M6

Disabled, On Fatal Error, On Fatal and Non-Fatal Errors

Note

 

The value On Fatal Error is not supported on C225 M8, C245 M8, and X215c M8 servers.

  • Disabled—eDPC support is turned off, and the system does not take any action to disable downstream links in response to errors.

  • On Fatal Error—eDPC is enabled only for fatal errors.is not supported on Cisco UCS C225 M8, Cisco UCS C245 M8, and X215c M8 servers.

  • On Fatal and Non-Fatal Errors—eDPC is enabled for both fatal and non-fatal errors.

Speculative Lock

The confl_lock metric counts how many times lock conflicts occur.

6.0(2x)

C220 M8, C240 M8, X210c M8, X410c M8, XE1X0M8

Enabled, Disabled

CPU Frequency Control

Indicates adjusting the speed of the CPU to find a good balance between how fast it works and how much power it uses.

6.0(2x)

C245 M8, C225 M8, X215c M8

Auto, Enabled, Disabled


Note

For Local APIC Mode Bios token, Compatability values are not supported for AMD EPYC 7XX2 series.