Trusted Platform
The following table lists the trusted platform BIOS settings that you can configure through a BIOS policy or the default BIOS settings:
Name |
Description |
Supported Attributes |
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Versions |
Platforms |
Values |
Dependencies |
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Multikey Total Memory Encryption (MK-TME) |
MK-TME allows you to have multiple encryption domains with one with own key. Different memory pages can be encrypted with different keys. |
4.2(1) nnd later |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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Software Guard Extensions (SGX) |
Allows you to enable Software Guard Extensions(SGX) feature. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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Total Memory Encryption (TME) |
Allows you to provide the capability to encrypt the entirety of the physical memory of a system. |
4.2(1) and later |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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Select Owner EPOCH Input Type |
Allows you to change the seed for the security key used for the locked memory region that is created. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
SGX Owner EPOCH activated, Change to New Random Owner EPOCHs, Manual User Defined Owner EPOCHs, SGX Owner EPOCH deactivated
|
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SGX Auto MP Registration Agent |
Allows you to enable the registration authority service to store the platform keys. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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SGX Epoch 0 |
Allows you to define the SGX EPOCH owner value for the EPOCH number designated by 0. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
0 - ffffffffffffffff with a step size of 1 |
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SGX Epoch 1 |
Allows you to define the SGX EPOCH owner value for the EPOCH number designated by 1. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
0 - ffffffffffffffff with a step size of 1 |
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SGX Factory Reset |
Allows the system to perform SGX factory reset on subsequent boot. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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SGX PubKey Hashn where n ranges from 0 to 3. |
Allows you to set the Software Guard Extensions (SGX) value. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
SGX PUBKEY HASH0, SGX PUBKEY HASH1, SGX PUBKEY HASH2, SGX PUBKEY HASH3
|
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SGX Write Enable |
Allows you to enable SGX Write feature. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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SGX Package Information In-Band Access |
Allows you to enable SGX Package Info In-Band Access. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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SGX QoS |
Allows you to enable SGX QoS. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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SHA-1 PCR Bank |
The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 1 or SHA-1 PCR Bank allows to enable or disable TPM security. |
4.2(1) and later |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, C125 M5, B200 M6, C220 M6, C240 M6, X210c M6, C225 M6, C245 M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M7, C240 M7, X210c M7, X410c M7, C225 M8, C245 M8, X215c M8, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled
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If the Security Device Support is disabled then the entire TPM operation will fail. |
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SHA256 PCR Bank |
The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 256-bit or SHA-256PCR Bank allows to enable or disable TPM security. |
4.2(1) and later |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, C125 M5, B200 M6, C220 M6, C240 M6, X210c M6,C225 M6, C245 M6,C220 M7, C240 M7, X210c M7, X410c M7,C220 M7, C240 M7, X210c M7, X410c M7,C225 M8, C245 M8, X215c M8,C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
If the Security Device Support is disabled then the entire TPM operation will fail. |
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SHA384 PCR Bank * |
The Platform Configuration Register (PCR) is a memory location in the TPM. Multiple PCRs are collectively referred to as a PCR bank. A Secure Hash Algorithm 384-bit or SHA-384PCR Bank allows to enable or disable TPM security. |
4.3(3a) and later |
B200 M6, C220 M6, C240 M6, X210c M6, C225 M6, C245 M6, C220 M7, C240 M7, X210c M7, X410c M7,C220 M7, C240 M7, X210c M7, X410c M7,C225 M8, C245 M8, X215c M8, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
If the Security Device Support is disabled then the entire TPM operation will fail. |
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Trusted Platform Module State |
Whether to enable or disable the Trusted Platform Module (TPM), which is a component that securely stores artifacts that are used to authenticate the server. |
4.2(1) and later |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, C125 M5, B200 M6, C220 M6, C240 M6, X210c M6, C225 M6, C245 M6, C220 M7, C240 M7, X210c M7, X410c M7,C225 M8, C245 M8, X215c M8, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
If the Security Device Support is disabled then the entire TPM operation will fail. |
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Trust Domain Extension |
Whether to enable or disable the Trust Domain Extension (TDX), which protects the sensitive data and applications from unauthorized access. |
4.3(3a) and later |
C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
To enable Trust Domain Extension, ensure that:
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TDX Secure Arbitration Mode (SEAM) Loader |
Whether to enable or disable the TDX Secure Arbitration Mode (SEAM) Loader, which helps to verify the digital signature on the Intel TDX module and load it into the SEAM-memory range. |
4.3(3a) and later |
X410c M7, X210c M7, C220 M7, C240 M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
To enable TDX Secure Arbitration Mode Loader, ensure that:
|
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TPM Pending Operation |
Trusted Platform Module (TPM) Pending Operation option allows you to control the status of the pending operation. |
4.2(1) and later |
C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C225 M8, C245 M8, X215c M8, C220 M8, C240 M8, X210c M8 |
None, TpmClear |
If the Security Device Support is disabled then the entire TPM operation will fail. |
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TPM Minimal Physical Presence |
Whether to enable or disable TPM Minimal Physical Presence, which enables or disables the communication between the OS and BIOS for administering the TPM without compromising the security. |
4.2(1) and later |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5, B200 M6, C220 M6, C240 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
If the Security Device Support is disabled then the entire TPM operation will fail. |
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Intel Trusted Execution Technology Support |
Whether to enable or disable Intel Trusted Execution Technology (TXT), which provides greater protection for information that is used and stored on the business server. |
4.2(1) and later |
B200 M5, B480 M5, C220 M5, C240 M5, C480 M5, S3260 M5,C240 M6, C220 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
TPM cannot be disabled unless TXT is disabled. |
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Security Device Support |
It controls the entire TPM functionality. |
4.2(3) and later |
C220M6, C240M6, C225M6, C245M6, B200M6, X210c M6, C225 M6, C245 M6, C220 M7, C240 M7, X210c M7, X410c M7, C225 M8, C245 M8, X215c M8,C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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DMA Control Opt-In Flag |
Enabling this token enables Windows 2022 Kernel DMA Protection feature. The OS treats this as a hint that the IOMMU should be enabled to prevent DMA attacks from possible malicious devices. |
4.2(2) and later |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
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LIMIT CPU PA to 46 Bits |
Limits CPU physical address to 46 bits to support the older Hyper-v CPU platform. |
4.2(2) and later |
C220 M6, C240 M6, B200 M6, X210c M6, C220 M7, C240 M7, X210c M7, X410c M7, C220 M8, C240 M8, X210c M8 |
Enabled, Disabled |
![]() Note |
SHA384 PCR Bank Bios token supports PID models UCS-TPM-002D and UCS-TPM-002D-D. |