Field Notice: FN74307 - Some Cisco Network Convergence System 540 Series Routers with Product IDs N540-24Q8L2DD-SYS and N540-24Q2C2DD-SYS May Exhibit Packet Drop Errors - Software Upgrade Recommended

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Updated:January 15, 2026
Document ID:FN74307

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High
Impact Rating:
High
First Published:
2026-Jan-15
Last Published:
2026-Jan-15
Revision:
1.0
Cisco Bug IDs:

Notice

THIS FIELD NOTICE IS PROVIDED ON AN "AS IS" BASIS AND DOES NOT IMPLY ANY KIND OF GUARANTEE OR WARRANTY, INCLUDING THE WARRANTY OF MERCHANTABILITY. YOUR USE OF THE INFORMATION ON THE FIELD NOTICE OR MATERIALS LINKED FROM THE FIELD NOTICE IS AT YOUR OWN RISK. CISCO RESERVES THE RIGHT TO CHANGE OR UPDATE THIS FIELD NOTICE AT ANY TIME.

Products Affected


Affected Product Name Description Comments
N540-24Q2C2DD-SYS NCS540-2x400G QSFP-DD+2x100G+24x25G  
N540-24Q8L2DD-SYS NCS540-2x400G QSFP-DD+8x50G+24x25G  




Defect Information


Defect IDHeadline
CSCwq28776N540-24Q8L2DD Arches Intermitten BIT flips causiing pkt Corruption.

Problem Description


Some Cisco Network Convergence System (NCS) 540 Series Routers with product IDs N540-24Q8L2DD-SYS and N540-24Q2C2DD-SYS may exhibit packet drop errors.


Background


A change in the component vendor's recommended operating values caused this issue. It has now been fixed, and devices shipping from manufacturing are equipped with correct voltage parameters.


Problem Symptom


Routers with product IDs N540-24Q8L2DD-SYS and N540-24Q2C2DD-SYS that are affected by the packet drop issue can be validated using the show environment voltage CLI command, as shown in the following example.

RP/0/RP0/CPU0:ios#show environment voltage
DDD MM DD HH:MM:SS UTC

Location: /RP0/CPU0

 Sensor               Value (mV)  Crit (Lo)  Minor (Lo)  Minor (Hi)  Crit (Hi)                   

 VH1_P12V             12486       10560      10800       13200       13440                                 
 VP8_METADX_AVDD_0V8  813         765        790         838         863                                   
 VP9_P1V0_IOFPGA      997         940        970         1030        1060                                  
 VP10_P1V8_IOFPGA     1805        1692       1746        1854        1908                                  
 VP11_P2V5            2507        2350       2425        2575        2650                                  
 VP12_P3V3            3308        3102       3201        3399        3498                                  
 VP13_P1V8            1797        1692       1746        1854        1908                                  
 VH1_CPU_12V          12501       10560      10800       13200       13440                                 
 VH4_CPU_5V_SDTBY     5008        4700       4850        5150        5300                                  
 VH2_GDDR6_1V25       1297        1222       1261        1339        1378                                  
 VP1_CPU_1V2_SDTBY    1207        1140       1164        1236        1272                                
 VP2_CPU_2V5_SDTBY    2515        2375       2425        2575        2650                                  
 VP3_CPU_3V3_SDTBY    3299        3135       3201        3416        3465                                  
 VP4_CPU_CORE_1V82    1786        1602       1711        1875        1966                                  
 VP5_CPU_PCH_1V5      1494        1425       1455        1545        1590                                  
 VP6_CPU_DDR_VTT_0V6  597         558        582         618         642                                   
 VP7_CPU_DDR_1V2      1195        1140       1164        1236        1275                                  
 VP8_CPU_2V5          2498        2375       2425        2575        2750                                  
 VP9_CPU_1V05         1047        987        1019        1076        1092                                  
 VP10_CPU_1V3         1295        1235       1261        1339        1378                                  
 VH3_GDDR6VPP_1V8    1799        1692       1746        1854        1908                                  
 VP11_CPU_1V7         1694        1615       1649        1751        1802                                  
 VP12_CPU_3V3         3301        3168       3218        3399        3465                                  
 P1V8_Q2A_VOUT        1794        1692       1746        1854        1908                                  
 P1V25_Q2A_VOUT       1291        1222       1261        1339        1378                                  
 VH4_02A_0V88         880         836        854         898         915                                   
 P0V82_Q2A_VOUT       720         707        722         927         977         
 P1V8_VOUT            1800        1692       1746        1854        1908                                  
 VP1_Q2A_XVDD1P8      1799        1692       1746        1854        1908                                  
 P3V3_VOUT            3304        3135       3201        3416        3465                                  
 P0V8_Q2A_SRDS_VOUT   801         752        776         824         848                                   
 VP2_02A_TVDD1P2      1198        1128       1152        1236        1260                                  
 P0V8_METDX1_VOUT     777         733        757         824         848                                   
 VP3_Q2A_XVDD0P8      799         760        772         828         836                                   
 P1V82_CPU_CORE_VOUT  1787        1692       1746        1854        1908                                  
 P1V2_CPU_VOUT        1197        1140       1164        1236        1275                                  
 VP4_Q2A_VDCC_0V82    718         707        722         927         977
 P1V05_CPU_VOUT       1050        987        1019        1076        1092                                  
 VP5_METADX_0V8       785         733        757         824         848

The voltage output  of P0V82_Q2A_VOUT and VP4_02A_VDCC_0V82 of 718 and 720 in the example indicates the failure signature described in this field notice.The voltage output of less than 760 can be considered as failure signature of the issue described in the field notice.


Workaround/Solution


Cisco recommends installing the SMU listed in the following table for routers that are deployed with Cisco IOS XR Software Releases. The fix is incorporated into base Cisco IOS XR Software releases 25.2.2 and later.

Cisco IOS XR Software Release SMU Type SMU Status SMU Download Instructions
7.11.2 Reload Posted
  1. Go to the Cisco Software Download page.
  2. Choose Routers > Service Provider Edge Routers > Network Convergence System 540 Series Routers.
  3. Choose the appropriate PID.
  4. Click IOS XR Software Maintenance Upgrades (SMU).
  5. From the left navigation pane, choose the software release.
  6. Install Hitless/Optional SMU, N540-24Q8L2DD Arches Intermittent BIT flips causing pkt Corruption.
24.4.2 Reload Posted
24.3.2 Reload Posted
24.2.2 Reload Posted
24.1.2 Reload Posted

Cisco does not recommend RMA for the issue observed as the issue can be fixed with the solution provided.


Revision History


VersionDescriptionSectionDate
1.0Initial Release—2026-JAN-15

For More Information

For further assistance or for more information about this field notice, contact the Cisco Technical Assistance Center (TAC) using one of the following methods:

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