Cisco Silicon One G100 Data Sheet
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Bias-Free Language
The documentation set for this product strives to use bias-free language. For the purposes of this documentation set, bias-free is defined as language that does not imply discrimination based on age, disability, gender, racial identity, ethnic identity, sexual orientation, socioeconomic status, and intersectionality. Exceptions may be present in the documentation due to language that is hardcoded in the user interfaces of the product software, language used based on RFP documentation, or language that is used by a referenced third-party product. Learn more about how Cisco is using Inclusive Language.
The silicon industry has always been plagued with the trichotomy of switching silicon, routing line card silicon, and routing fabric silicon. Using these three basic building blocks, silicon and system vendors created unique architectures tuned for individual markets and industries. Consequentially, forcing customers to consume and manage these disjointed and dissimilar products caused an explosion in complexity, CapEx, and OpEx for the industry.
The Cisco Silicon One™ architecture ushers in a new era of networking, enabling one silicon architecture to address a broad market space, while simultaneously providing best-of-breed devices.
At 25.6 Tbps, the Cisco Silicon One G100 builds on the groundbreaking technology of the Cisco Silicon One Q200L but brings the efficiency and flexibility of Cisco Silicon One and 7 nm to new levels by enabling 1 Rack Unit (RU) 64x400GE spine and leave switches.
The Cisco Silicon One G100 processor is a 25.6-Tbps, full-duplex, standalone switching processor that can be used to build fixed form factor switches ideally targeted for web-scale data center spine and leaf applications. The G100 can be configured in one of two modes:
● 25.6-Tbps, full-duplex, standalone switching processor
● 25.6-Tbps, full-fuplex, fabric element
Cisco Silicon One G100 and P100 can be used together to build a wide range of products covering fixed form factor routers and switches, modular chassis routers and switches, and multipetabit disaggregated routers and switches.
Form Factors
Table 1. Architectural characteristics and benefits
| Feature |
Benefit |
| Unified architecture across multiple markets |
Greatly simplifies customer network infrastructure deployments |
| Unified SDK across market segments and applications |
Provides a consistent point of integration for all applications across the entire network infrastructure |
| High-performance switching silicon |
Achieve line rate at small packet sizes |
| Power-efficient switching silicon |
The power efficiency of 7 nm and the Cisco Silicon One architecture optimized for the high-bandwidth web-scale switching market |
| Large and fully unified packet buffer |
Fully shared on-die packet buffer |
| Switching efficiency with programmable features |
Addresses the requirements of web-scale providers’ switching applications without sacrificing features and programmability |
| Run-to-completion network processor |
Provides feature flexibility without compromising performance or power efficiency |
| P4 programmable |
A programmable processor to allow for rapid feature development |
Flexibility and performance for next-generation web-scale networks
Block Diagram
Features
● 256 112G SerDes; each can be configured independently to operate in 10G/25G/50G/100G using NRZ or PAM4 modulation
● Flexible port configuration supporting 10/25/40/50/100/200/400/800/1.6T Gbps
● Large, fully shared, on-die packet buffer
● 1588v2 and SyncE support with nanosecond-level accuracy
● On-chip, high-performance, P4-programmable host NPU for high-bandwidth offline packet processing (for example, OAM processing and MAC learning)
● Multiple embedded processors for CPU offloading
Traffic management
● Large pool of configurable queues
● Support for ingress and egress traffic mirroring
● Support for link-level (IEEE802.3x), PFC priority-level (802.1Qbb) flow control and ECN marking
● Support of port extenders
NPU
● Run-to-completion, distributed, P4-programmable NPU architecture
● Line rate at very small packets with complex packet processing
● Web-scale optimized and shared NPU fungible tables
● Support of demanding packet processing features without impacting data rate
● Support of simple packet processing features while optimizing power and latency
Load balancing
● Flow load balancing using ECMP or LAG
● Dynamic flowlet load balancing with ability to detect and handle elephant flows
● Packet-by-packet load balancing, creating an optimal, flow-independent, end-to-end scheduled and lossless fabric
Instrumentation and telemetry
● Programmable meters used for traffic policing and coloring
● Programmable counters used for flow statistics and OAM loss measurements
● Programmable counters used for port utilization, microburst detection, delay measurements, flow tracking, elephant flow detection, and congestion tracking
● Traffic mirroring: (ER)SPAN on drop
● Support for sFlow and NetFlow
● Support for in-band telemetry
SDK
● APIs provided in both C++ and Python
● SAI and SONiC support
● Configurability via high-level networking objects
● Distribution-independent Linux packaging
● Robust simulation environment enables rapid feature development
● CPU packet I/O through native Linux network interfaces
P4 programmability
● Application development is handled by a P4-based IDE programming environment
● At compilation, the P4 application generates low-level register/memory access APIs and higher-level SDK Application APIs
● Provides application support for a wide range of data center, service provider, and enterprise protocols
● Ability to develop the SDK and applications running over the SDK over a simulated Cisco Silicon One device
Cisco P4 application
Due to Silicon One’s extensible P4 programming toolkit, we are always adding features to address new markets and new customer requirements; however, a sample of the features that are currently available with the P4 code is provided below:
|
● MPLS
● Ethernet Switching
◦ 802.1d, 802.1p, 802.1q, 802.1ad
● IP Tunneling
◦ IP in IP ◦ GRE ◦ VXLAN
● Integrated Routing and Bridging (IRB)
● HSRP/VRRP
● Policy-Based Routing
● Security and QoS ACLs
● ECMP and LAG (802.3ad)
● Multicast
◦ IGMP
● NAT/PAT
● Protection (Link/Node/Path and TI-LFA)
|
● QoS Classification and Marking
● Congestion Management
● Telemetry
◦ NetFlow, sFlow ◦ In-Band Telemetry ◦ (ER)SPAN ◦ Packet Mirroring with Appended Metadata ◦ Lawful Intercept
● Warmboot
● DDoS Mitigation
◦ Control-Plane Policing ◦ BGP Flowspec
● Timing and Frequency Synchronization
◦ SyncE ◦ 1588 |
Information about Cisco’s Environmental, Social, and Governance (ESG) initiatives and performance is provided in Cisco’s CSR and sustainability reporting.
Table 2. Cisco environmental sustainability information
| Sustainability Topic |
Reference |
|
| General |
Information on product-material-content laws and regulations |
|
| Information on electronic waste laws and regulations, including our products, batteries, and packaging |
||
| Information on product takeback and reuse program |
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| Sustainability inquiries |
Contact: csr_inquiries@cisco.com |
|
| Material |
Product packaging weight and materials |
Contact: environment@cisco.com |
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Table 3. Document history
| New or Revised Topic |
Described In |
Date |
| Added fabric element support |
- |
October 2021 |