A separate external time-division multiplexing (TDM) circuit is required to provide synchronized timing to multiple remote network elements (NEs) for packet transport networks like Cisco Carrier Packet Transport system. The Synchronous Ethernet (SycnE) feature addresses this requirement by providing effective timing to the remote NEs through a packet network without using an external circuit for timing.

With Ethernet equipment gradually replacing existing Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) equipment in service-provider networks, frequency synchronization is required to provide high-quality clock synchronization over Ethernet ports. The SyncE feature provides the required synchronization at the physical level. Operation messages maintain SyncE links and ensure that a node always derives timing from the most reliable source. SyncE uses the Ethernet Synchronization Message Channel (ESMC) to enable traceability of the best clock source to correctly define the timing source and prevent a timing loop.

SyncE provides the Ethernet physical layer network (ETY) level frequency distribution of known common precision frequency references. Clocks for use in SyncE are compatible with the clocks used in the SONET/SDH synchronization network. To achieve network synchronization, synchronization information is transmitted through the network via synchronous network connections with performance of egress clock. In SONET/SDH the communication channel for conveying clock information is SSM, and in SyncE it is the ESMC.

SyncE is a standard for distribution of frequency over Ethernet links. Other standards (IEEE Std. 1588 Precision Time Protocol [PTP], IETF Network Time Protocol [NTP], etc.) have been and are being developed or enhanced for high-quality time distribution and Adaptive Clock Recovery (ACR) requirements.

To maintain the timing chain in SONET/SDH, operators often use SSM. Information provided by SSM Quality Levels (SSM-QL) helps a node derive timing from the most reliable source and prevent timing loops. The SONET/SDH header has a QL information present in the S1 bytes of its header. Hence, the SONET/SDH does not require any specific channel for QL information exchange. As the Ethernet does not have the QL information in its header, it requires ESMC for QL information. Because Ethernet networks are not required to be synchronous on all links or in all locations, a specific channel, the ESMC channel defined in G.8264, provides this service. ESMC is composed of the standard Ethernet header for an organization-specific slow protocol, the ITU-T OUI; a specific ITU-T subtype; an ESMC-specific header; a flag field; and a type, length, value (TLV) structure: the use of flags and TLVs aimed at improving the management of Synchronous Ethernet links and the associated timing change.

• ITU-T G.8261: Timing and synchronization aspects in packet network

• ITU-T G.8262: Timing characteristics of Synchronous Ethernet equipment slave clock

• ITU-T G.8264: Distribution of timing through packet networks

• ITU-T G.781: Synchronization layer functions

These standards specify the jitter and wander tolerances, supported frequencies, clock specifications (Synchronous Ethernet Equipment Clocks [EECs] are defined to ensure compatibility with SONET/SDH clocks detailed in ITU-T G.813 and G.812 or Telcordia GR-1244-CORE), clock selection logic, possible clock quality levels, error responses, noise tolerances, noise generation and transfer limits, holdover performance, deployment scenarios, interworking requirements, clock selection process, SSM support, and a new ESMC (which allows interworking with existing SONET/SDH infrastructure by allowing the SyncE links to convey the SSM quality level as defined in ITU-T G.707, G.781, Telcordia GR-253-CORE, and ANSI T1.101).

The clock selection algorithm of SyncE runs on the controller card of the Cisco CPT. The controller card has a Digital Phase Lock Loop (DPLL) that validates the clock for OOB (Out of Bound) frequency and then based on the clock stability and Quality Level (QL) selects the appropriate clock. All the clocks selected as reference are sent to the controller card for validation and selection. However, if an appropriate clock is not found, the controller card that has an ST3 internal clock is used as a FreeRunning clock to drive the system.

CPT supports a maximum of three clock references (per node) to be configured including BITS, 10G ports on the fabric or line card, and 1G CPT-50 ports. The clock source can be configured on any of the10G ports of the fabric, line card, and 1G ports in CPT-50. The fabric XFP port in OTN mode can also be configured as the clock source and does not require Ethernet Synchronization Message Channel (ESMC) because it derives the QL information from the OTN OTU2E RES header. The XFP ports in OTN mode transmits the SSM-QL information in OTN OTU2E RES header.

ESMC can be enabled on any port. Administrative configuration of QL is used to support non-ESMC legacy clock sources (ITUT G.8264 /10.2) or to override a QL. CPT needs a clock to be stable for 140 seconds to use it as HoldOver.

SyncE can be used with TNC, TSC, TNC-E, and TSC-E as a controller card in CPT.

• SyncE is supported for all pluggables except copper GE SFPs.

• Clock source per slot supported is only one.

• Clock that is persistent for less than 140 seconds then the clock cannot go to the holdover state.

• Controller card handles up to three clock sources and selects the best of the three clock sources.

• Clock sources that are configured and the ports configured with "ESMC Enabled" must be disabled when changing the clock mode.

• SyncE phase transients fail mask during hardware reset of the TNC-E card.

• Generation 1 to Generation 2 or SDH mode to SONET mode (or vice-versa) migration requires all the clock sources and ESMC enabled ports to be deselected and the generation/clock mode, changed.

Network clocking uses the Synchronization Status Messages (SSM) mechanism to exchange the Quality Level (QL) of the clock between the network elements. In Ethernet, Ethernet Synchronization Message Channel (ESMC) is used for SSM exchange.

The clock selection algorithm selects the best available synchronization source from the nominated sources. This algorithm exhibits nonrevertive behavior among the clock sources with the same QL value, and always selects the signal with the best QL value. For clock option SDH, the default is revertive, and for clock option SONET, the default is nonrevertive.

The CPT supports the following clock source references:

Line Card Clock Source

One SyncE clock source per line card is supported. In Cisco CPT-600, a maximum of six clock sources are available for selection excluding the BITS; In Cisco CPT-200, a maximum of two clock sources are available for selection excluding BITS.

Note	The CPT supports a maximum of three clock references.

For example, more than one clock source per line card (inclusive of all the Cisco CPT-50 fanout ports) cannot be selected. If a Cisco CPT-50 1G port is selected as a clock source, no other clock source from any other Cisco CPT-50 fanout from that slot (where the former CPT-50 was fanned out) nor can any port from the line card can be selected.

• Holdover Mode—In this mode, all external or line timing references are lost and the clock uses timing data referenced while in normal operating mode to control its output signal. However, holdover frequency drifts over time until a timing reference becomes available. If the previous timing reference was available for less than 140 seconds before it was lost, TCC enters the Free-running mode when the timing reference is lost. This mode is better than the Free-running mode because it uses the average of 140 seconds of data from the last qualified timing reference to augment its internal clock. TCC remains in this mode until a reference becomes available to switch, or the drift is out of bounds. Traffic is guaranteed to be uninterrupted by a transition to the Holdover mode for the first 24 hours.

• Free-running Mode—This mode mode only references the internal clock on the TCC card. It is also the default mode when other references are lost, even when it is not specifically provisioned as a reference. Ensure that your network does not operate with the internal clock of the TCC card as the only or primary timing source.

• External—Only external clock can be used as a source. The external clock source can be configured as Internal, BITS-IN1, and BITS-IN2.

• Line—Internal controller card clock (ST3 in SONET, and SEC in SDH) or line card ports (10G ports in fabric or line card and 1G ports in CPT-50) can be selected as clock source.

• Mixed—Both External and Line clock sources can be configured.

The switching of timing references can be made revertive or non-revertive. In non-revertive switching, a switch to an alternate reference is maintained even after the original reference has recovered from the failure that caused the switch. However, that the node should switch back to the original reference (rather than enter the Holdover) if the original reference has recovered from its failure and the alternate reference subsequently fails. The clock enters Holdover only when all references fail, regardless of the revertive setting. In revertive switching, the clock switches back to the original reference after that reference recovers from the failure, independent of the condition of the alternate reference. In CPT, support for revertive and non-revertive clock source is on a slot basis as CPT does not support more than one clock source per line card slot.

If the primary external source fails, the clock card enters holdover mode. After a few seconds, it switches over to the secondary external source. The clock card switches back to the primary external source only when it becomes available.