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The Cisco Nexus SmartNIC+ V9P (formerly ExaNIC V9P) is an FPGA based network application card, specifically optimized for low-latency and high density datacenter applications. The device is built around a powerful Virtex Ultrascale Plus (VU9P) FPGA, packaged into a compact, half-height half-length, form factor, featuring dual QSFP-DD interfaces (8 lanes each) and 9GB of DDR4 DRAM.
Installation of the SmartNIC+ V9P is similar to other Cisco Nexus SmartNIC devices. This page should be used in conjunction with the SmartNIC Installation section.
The SmartNIC+ V9P is available only in a passively cooled variant. This means that suitable airflow must be provided by the enclosing server. As an example, Dell R630 and R640 servers are suitable for this use case. It is expected that any similar server platform will be sufficient.
The firmware recovery procedure for the SmartNIC+ V9P differs from other SmartNIC devices and requires JTAG access to the device. To recover an SmartNIC+ V9P:
xcvu9p
device.NOREBOOT=1
. A bitfile of the native_nic_example
which can be used for this purpose is available via Cisco TAC.The SmartNIC+ V9P should now be recovered with regular NIC functionality.
The SmartNIC+ V9P features an onboard USB to JTAG adapter. Users can plug the supplied USB cable into the 4 pin USB header (J5). It will appear as a supported JTAG device in Xilinx Vivado.
A small header (J4) is on the SmartNIC+ V9P that exposes 4 bits of user GPIO. Please create a case with Cisco TAC for further details on this interface.
An MCX connector is onboard for PPS in/out time synchronization. Due to size & area restrictions, this connector could not be placed on the PCIe bracket. To use the connector, it is suggested that users run a small loom from the MCX connector to just outside the bracket for connection to a PPS network.
A Firmware Development Kit is available for the SmartNIC+ V9P to simplify FPGA development, which includes Cisco's low latency PCS/MAC and DMA engine. Further details on the FDK can be found on our FDK Documentation Site.
For customers using their own IP, the following hardware specific notes may be helpful:
PERSTN0
is inverted on the PCB. When using the Xilinx PCIe core, the System Reset Polarity dropdown will need to be set to ACTIVE HIGH.161M reference clocks are supplied to the following locations:
The following GTY transceiver channels have their polarity inverted on the PCB - the transceiver IP core will need to have rx_pol
/tx_pol
set for these:
While designing the application for V9P, please ensure that the power requirement for the VccBRAM+VccINT_IO should stay less than 1A.