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Release Notes for the Catalyst 8540 MSR ATM Router Module FPGA Image Release 2.4

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Release Notes for the Catalyst 8540 MSR ATM Router Module FPGA Image Release 2.4

Release Notes for the Catalyst 8540 MSR ATM Router Module FPGA Image Release 2.4

July 18, 2000

Catalyst 8540 MSR ATM router module FPGA image name fi-c8540-arm.A.2-4

This document describes the features and caveats for the Cisco field-programmable gate array (FPGA) functional image, fi-c8540-arm.A.2-4, for the ATM router modules used with the Catalyst 8540 MSR.

This version of the ATM router module FPGA image fixes caveat CSCdp98040 listed in the "Caveats" section later in this release note.

Note   The ATM router module FPGA image is now separate from the 2-port Gigabit Ethernet FPGA image. Beginning with the ATM router module FPGA Release 2.4 and going forward, the FPGA images will remain separate.

Contents

This release note includes the following sections:

Introduction

The ATM router module provides the Catalyst 8540 MSR with high-speed internetworking between the Layer 2 and Layer 3 network topologies. The ATM router module is a full-width module that occupies an entire slot in the ATM switch. You can install up to two ATM router modules in slots numbered 0-3 and 9-12 in the Catalyst 8540 MSR chassis. The ATM router module is hot-swappable.

Determining the FPGA Image Release Installed on Your Catalyst 8540 MSR ATM Router Module

This section describes the process used to determine the FPGA functional image version installed on your ATM router module.

To display the functional image version of an ATM router module, use the following command in privileged EXEC mode:

Command Purpose

show functional-image-info {slot number | subslot slot/subslot}

Displays the functional image information.


Example

The following example shows the FPGA functional image information for the ATM router module in slot 0:

Switch# show functional-image-info slot 0

 
Functional Version of the FPGA Image: 2.4
 #Jtag-Distribution-Format-B
 #HardwareRequired:A06(2.0-10,3.0-100,4.0-100),A0C(1.0-100,2.0-100,3.0-100,4.0-100)
 
   
 #FunctionalVersion: 2.4
 #Sections: 1
 #Section1Format: MOTOROLA_EXORMAX
 
Copyright (c) 1996-00 by cisco Systems, Inc.
  All rights reserved.
  generated by:       gachan
  on:                 Thu Jun  1 14:52:05 PDT 2000
  using:              /vob/cougar/bin/jtag_script Version 1.13
  config file:        giga_epam.jcf
 
  Chain description:
  Part type Bits Config file
  xc4010    3    /vob/cougar/custom/tigershark_2port/syn_giga/giga_epam_r.bit
  xla4062   3    /vob/cougar/custom/tigershark_2port/xilinx_vix/route_m31i_0531/gx_vix_af.bit
  xla4062   3    /vob/cougar/custom/tigershark_2port/xilinx_vix/route_m31i_0531/gx_vix_af.bit
  xla4062   3    /vob/cougar/custom/tigershark_2port/eth/gx_eth.bit
  xla4062   3    /vob/cougar/custom/tigershark_2port/eth/gx_eth.bit
  XC4005    3    /vob/cougar/custom/common/jtcfg/xil/jtcfg_r.bit
  Number devices             = 6
  Number of instruction bits = 18
 
  FPGA config file information:
  Bitgen date/time  Sum   File
  1999/05/10 16:14:16 21062 /vob/cougar/custom/tigershark_2port/syn_giga/giga_epam_r.bit
  2000/06/01 12:16:38 61853 /vob/cougar/custom/tigershark_2port/xilinx_vix/route_m31i_0531/gx_vix_af.bit
  2000/06/01 12:16:38 61853 /vob/cougar/custom/tigershark_2port/xilinx_vix/route_m31i_0531/gx_vix_af.bit
  98/11/19 03:16:57 38973 /vob/cougar/custom/tigershark_2port/eth/gx_eth.bit
  98/11/19 03:16:57 38973 /vob/cougar/custom/tigershark_2port/eth/gx_eth.bit
  98/06/11 16:56:44 49904 /vob/cougar/custom/common/jtcfg/xil/jtcfg_r.bit
 
 #End-Of-Header

Updating to a New Release

For detailed FPGA image upgrade instructions, see the "Maintaining Functional Images" section of the "Managing Configuration Files, System Images, and Functional Images" chapter of the ATM Switch Router Software Configuration Guide.

Caveats

This section lists the caveats and corrected caveats for each release. Use the table to determine wether a particular caveat applies to your FPGA functional image release, or whether a particular caveat was corrected in your FPGA or firmware image release. In the table, "Y" indicates a corrected caveat, "N" indicates an open caveat, and "-" indicates the corrected caveat has been carried over from the previous release. These caveats are described in detail in the next section "Caveat Symptoms and Workarounds."

Table 1 lists the known caveats and corrected caveats for this ATM router module FPGA image.


Table 1: Catalyst 8540 MSR ATM Router Module FPGA Image Release Caveats Reference
DDTS Number FPGA Release fi-c8540-arm.A.2-4

CSCdp98040

Y


Caveat Symptoms and Workarounds

This section describes the closed caveats for this ATM router module FPGA functional image.

This carrier module FPGA image fixes the following known DDTS:

  • CSCdp98040

Symptom: The ATM router module does not come up with the Xylan LECs. This pertains to the ATM router module FPGA image version fi-c8540-2gpam.B.2-3 or previous.

Workaround: Upgrade the ATM router module FPGA image to fi-c8540-arm.A.2-4.

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