Digital signal level 3 (DS-3) supports speeds of up to 44.736 Mbps and is a popular link type for WAN backbone applications. DS-3 lines are designed to synchronously carry up to 28 DS-1 (T1) lines. The American National Standards Institute (ANSI) document T1.107-1998 defines the electrical specifications for DS-3 links.
E3 supports speeds up to 34.368 Mbps and is a popular link type for WAN backbone applications outside of North America.
Most DS-3 and E3 interfaces offer a choice of four framing formats. These formats differ in the number of overhead bytes, number of payload bytes, and method of delineating adjacent ATM cells.
This document reviews the four framing formats and explains how to troubleshoot any physical-layer line errors as displayed by the show controllers atm command.
There are no specific requirements for this document.
This document is not restricted to specific software and hardware versions.
For more information on document conventions, refer to the Cisco Technical Tips Conventions.
For ATM technology, this document uses the multiframe format described in G.704 recommendation.
A DS-3 bit stream is organized as a series of multiframes, known as M frames. Each M frame is partitioned into seven M subframes of 680 bits each. An M subframe is further partitioned into eight blocks of 85 bits each. An 85-bit block consists of 84 user information bits and one of these framing overhead bits:
P1, P2—P bits serve as a parity check to protect against bit errors as the frame traverses the physical wire.
X1, X2—X bits are used to indicate received errored multiframes to the remote end.
F1, F2, F3, F4—F bits serve as alignment signals used by the receiving equipment to identify the overhead bit positions. The values are F1 = 1, F2 = 0, F3 = 0, F4 = 1.
M1, M2, M3—M bits serve as a multiframe alignment signal used to locate all seven M-subframes, within the multiframe. The values are M1 = 0, M2 = 1, M3 = 0.
C bits used as bit staffing with M23 framing and as in-service end to end path performance monitoring with C-bit framing.
From a total of 4760 bits, each M-frame includes 4704 user bits and 56 framing-overhead bits.
For ATM technology, this document uses the basic frame structure described in G.832 or G.751 recommendations.
With G.832 the basic E3 frame structure has seven octets of overhead and 530 octets of payload. Overhead bytes are used for a frame alignment, error monitoring and maintenance.
With G.751, 4 four digital signals are Multiplexed at 8448 kbit/s speed
Two methods exist for mapping ATM cells into the DS-3 or E3 framing structure:
Physical layer convergence protocol (PLCP).
ATM direct mapping (ADM).
E3 using G.832 recommendation can use the ADM mapping only.
PLCP consists of subframes normally represented in technical documentation as a two-dimensional grid of rows and columns of cells and overhead bytes. Each row consists of 53 bytes of ATM cell and four bytes of framing overhead and management, as illustrated in this diagram:
In this diagram, POI stands for path overhead indicator, and POH stands for path overhead. A1 and A2 provide frame alignment and must follow a distinct pattern of ones and zeros.
PLCP was originally designed to pass timing information from the physical layer to a special higher layer to support isochronous services. Since ATM does not use these services, PLCP introduces additional overhead and ADM replaces PLCP.
ADM maps ATM cells directly into DS-3 or E3 frames. The header error check (HEC) field in the ATM five-byte header is used to identify the start of the initial cell in a frame. A receiving device examines the incoming bit stream and checks if a set of eight bits comprises a valid cyclic redundancy check (CRC) for the preceding 32 bits.
To understand why you would use ADM in preference to PLCP, look at the differences between the two protocols:
ADM = (672 bits per M-subframe) x (7 M-subframes) / (106.4 microseconds) = 44.21 Mbps
PLCP = (8000 frames per second) x (12 cells per frame) = 96,000 cells per second = 40.70 Mbps
PLCP - The ATM cells are in predetermined locations within each PLCP row. No additional method is needed to delineate ATM cells.
ADM - The header error control (HEC) field of the ATM cell header is used to delineate ATM cells.
Note: Cell delineation defines how a receiving device recognizes the start and end of an ATM cell.
You can configure Cisco ATM router and Catalyst switch interfaces with these framing formats depending on the specific hardware. It is important to note that specific hardware uses different defaults. For example, the default (and only option) on the CS-AIP-DS3 is cbitplcp, while the PA-A3-T3 and PA-A6-T3 use a default value of cbitadm. Take care to check the framing format when swapping hardware. Default parameters are not displayed in the running configuration.
Use the atm framing command to configure a non-default value. An interface must be shut/no shut for a change to take effect.
|Lightstream 1010 or Catalyst 85x0 PAM||Yes||Yes||Yes||Yes|
|Catalyst 5000 ATM Module||Yes||Yes||Yes||Yes|
* cbitadm requires Cisco IOS® Software Release 12.1(1)T or later.
|Lightstream 1010 or Catalyst 85x0 PAM||Yes||Yes||Yes|
Use the show atm interface atm and show controllers atm commands to view the currently active framing format.
AIP#show atm interface atm 1/0 ATM interface ATM1/0: AAL enabled: AAL5 , Maximum VCs: 2048, Current VCCs: 2 Tx buffers 256, Rx buffers 256, Exception Queue: 32, Raw Queue: 32 VP Filter: 0x7B, VCIs per VPI: 1024, Max. Datagram Size:4496 PLIM Type:E3 - 34Mbps, Framing is G.751 PLCP, TX clocking: LINE 31866 input, 27590 output, 0 IN fast, 0 OUT fast Rate-Queue 0 set to 34000Kbps, reg=0x4C0 DYNAMIC, 2 VCCs Config. is ACTIVE PA-A3#show controllers atm 1/0/0 ATM1/0/0: Port adaptor specific information Hardware is DS3 (45Mbps) port adaptor Framer is PMC PM7345 S/UNI-PDH, SAR is LSI ATMIZER II Framing mode: DS3 C-bit ADM No alarm detected Facility statistics: current interval elapsed 796 seconds lcv fbe ezd pe ppe febe hcse ---------------------------------------------------------------------- lcv: Line Code Violation be: Framing Bit Error ezd: Summed Excessive Zeros PE: Parity Error ppe: Path Parity Error febe: Far-end Block Error hcse: Rx Cell HCS Error
On interfaces other than the ATM Interface Processor (AIP), the show controllers atm command also displays active alarms and non-zero error counters, referred to the output as facility statistics. Non-zero values indicate a problem with the physical wire between this router interface and another network device, typically a switch in the ATM network provider's cloud.
If the framing type at two ends of an ATM link is mismatched, the ATM interface will be down. The show controller atm command reports Framer Out of Frame (FRMR OOF) and ATM Direct Mapping Out of Cell Delineation (ADM OOCD) defects, as illustrated in this output.
router#show controller atm 3/0 Interface ATM3/0 is down Hardware is RS8234 ATM DS3 [output omitted] Framer Chip Type PM7345 Framer Chip ID 0x20 Framer State RUNNING Defect FRMR OOF Defect ADM OOCD Loopback Mode NONE Clock Source INTERNAL DS3 Scrambling ON Framing DS3 C-bit direct mapping
Troubleshoot OOF and OOCD errors by confirming the framing configuration at each end. Use the atm framing command to configure and experiment with other framing types.
Request for Comments - RFC 1407 defines DS-3 and E3 alarms and errors. Refer to Troubleshooting Line Problems and Errors on DS-3 and E3 ATM Interfaces for guidance.
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Refer to Cisco Technical Tips Conventions for information on conventions used in this document.