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Cisco Nexus X100 SmartNIC K3P-Q Data Sheet

Data Sheet

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Updated:August 26, 2020

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    (339.1 KB)
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Updated:August 26, 2020
 

 

Ultra-low latency network interface card

High-density, ultra-low latency

The Cisco Nexus® X100 SmartNIC K3P-Q is a high-density NIC, specifically optimized for low latency operation.

Features 2x QSFP28 ports for a total of eight Ethernet links and software trigger-to-response latencies as low as 596ns. This is up to 20 percent faster than previous Cisco Nexus SmartNIC models, making it one of the fastest high-density network adapter in the market. Users will find that this drop-in replacement NIC accelerates tick-to-trade performance to previously unachievable speeds, increasing the efficacy and profitability of software-based trading systems.

Advanced software programmability

The Cisco Nexus X100 SmartNIC K3P-Q provides the most powerful programmable software interface on the market.

Programmability features include:

      Zero-latency cost hardware flow steering: allowing users to steer and prefilter important traffic to the right memory and CPU core with no latency penalty.

      Cut-through receive: This mechanism allows software to process packet fragments as they arrive from the wire, while packet tails are still in flight. This is especially effective for slow line speeds (for example, 1GbE). The Cisco Nexus X100 SmartNIC K3P-Q software API puts users well ahead of traditional store-and-forward NIC designs to make better decisions, faster.

      ExaSOCK TCP/IP acceleration: Unmodified socket applications can benefit from the speed and power of the Cisco Nexus X100 SmartNIC K3P-Q using ExaSOCK. ExaSOCK is an in-place TCP/IP socket acceleration system. ExaSOCK’s Extension API allows it to seamlessly interoperate with the X100 SmartNIC’s transmit preloading feature, described below.

      Preloaded packet transmit: The Cisco Nexus X100 SmartNIC K3P-Q allows users to preload transmit frames, saving 60ns from the transmit path. The X100 SmartNIC K3P-Q features enlarged packet transmit buffers allowing many more frames to be preloaded, leading to more versatile transmission choices.

      High-resolution timestamps: Four-nanosecond timestamps are applied to every received packet and the most recently transmitted packet. The Cisco Nexus X100 SmartNIC K3P-Q also features out of the box support for IEEE1588 (PTP) and high-speed capture to disk using free and open-source Exact-Capture software.

25GbE ready

The Cisco Nexus X100 SmartNIC K3P-Q is a pure FPGA-based network adapter that is 25/100GbE ready.

Field Programmable Gare Array (FPGA) network adapters extend the useful life of the Cisco Nexus X100 SmartNIC K3P-Q by allowing new features and speed enhancements to be downloaded into the device after deployment.

All-FPGA design

The Cisco Nexus X100 SmartNIC K3P-Q is built using the latest generation Xilinx UltraScale+ FPGA

It optionally ships with 9GB of DDR4 memory for custom use. It is a compact adapter in a low-profile form-factor. Users can benefit from the all-FPGA design by offloading critical network processing functions directly into the NIC, while maintaining the ease of use and administration of a production-grade network adapter.

Cisco Nexus X100 SmartNIC (K3P-Q)

Figure 1.            

Cisco Nexus X100 SmartNIC K3P-Q

Performance

Typical latency, raw frames:1

      64 bytes: 714 ns

      256 bytes: 927 ns

Typical latency, raw frames with preloaded TX buffer:1

      64 bytes: 653 ns

      256 bytes: 690 ns

Typical latency, UDP:2

      14 bytes: 828 ns

      256 bytes: 1.11 µs

Typical latency, TCP:2

      14 bytes: 869 ns

      256 bytes: 1.13 µs

Timestamping

Timestamp resolution:

      4ns

Timestamp availability:

      All received frames, most recently transmitted frame

Time synchronization:

      Host, hardware assisted PTP, optional PPS

PPS input/output:

      3.3V CMOS, selectable 50ohm termination

Other features

Capture:

      Line-rate capture to disk

Flow steering:

      64 IP rules per port

      64 MAC rules per port

FPGA Development Kit:

      Add custom user logic to FPGA

      Fully integrated with drivers and utilities

      Xilinx Ultrascale+ XCKU3P-2

      9GB DDR4 (optional)

General

Form factor:

      Low-profile PCI Express Card

      117x68mm (4.65x2.67in)

Recovery:

      Manual firmware recovery button

Ports:

      2x QSFP28

      SMA for PPS in/out

Data rates:

      40GbE3, 25GbE3, 10GbE, 1GbE, 100M Fast Ethernet

Supported media:

      Fiber (100GBASE-SR4, 100GBASE-LR4, 100GBASE-CX4), QSFP(+/28) Direct Attach

Host interface:

      PCIe x8 Gen 3 @ 8.0 GT/s per lane

Operating systems:

      Linux x86_64 (all distributions)

      Windows

Footnote

1.Latencies are median latencies for raw frames from wire-userspace-wire via the libNexus SmartNIC library, on a 3.5Ghz Intel ® Ivy Bridge processor.
2.Latencies are median half-roundtrip time latencies for the sockperf benchmark using the exasock socket acceleration library. More information about benchmarking methodology is available on request.

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Information about Cisco’s environmental sustainability policies and initiatives for our products, solutions, operations, and extended operations or supply chain is provided in the “Environment Sustainability” section of Cisco’s Corporate Social Responsibility (CSR) Report.

Reference links to information about key environmental sustainability topics (mentioned in the “Environment Sustainability” section of the CSR Report) are provided in the following table:

Sustainability topic

Reference

Information on product material content laws and regulations

Materials

Information on electronic waste laws and regulations, including products, batteries, and packaging

WEEE compliance

Cisco makes the packaging data available for informational purposes only. It may not reflect the most current legal developments, and Cisco does not represent, warrant, or guarantee that it is complete, accurate, or up to date. This information is subject to change without notice.

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