Revised April 24, 2007
June 18, 1999
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Certain chassis configurations result in 2-port Gigabit Ethernet cards not coming up when installed with 10/100 EPAMs. These same cards work when moved to other slots in the chassis.
Read/write hardware errors occur in Catalyst 8540s when 8-port Gigabit Ethernet cards are installed with 10/100 EPAMs that have a field programmable gate array (FPGA) image earlier than fi-c8540-epam.A.3-2.
Installing just the 10/100 and 100FX cards may also cause bus error problems. These problems are fixed by the new FPGA image.
If a Fast Ethernet interface module is installed on an active switch, cells become stuck in the switch fabric when a second route processor (RP) module is inserted into the chassis or if the active RP is switched to standby.
Under certain conditions when a 16-port 10/100 EPAM and a 2-port Gigabit Ethernet card are in a system, a race situation may appear generating a bus error.
An 8-port gigabit PAM development showed a bug in the 10/100 FPGA where the 10/100 card would respond to the packet targeted toward the 8-port gigabit card causing read/write errors.
The problem was noticed and was easily reproduced when the Gigabit Ethernet and 10/100 FE combination was installed. The problem was traced to bus errors; this was resolved by the FPGA. Further analysis revealed that the bus errors can occur even without the Gigabit Ethernet combination, and that the problem can manifest itself in different ways. For example, certain Cisco IOS® Software commands would have no affect and some IPCs from RP to the line cards would be wrong.
During testing of the redundancy feature on the Catalyst 8540 CSR, it was discovered that this problem could occur.
With a 2-port gigabit card installed in some configurations that include the 10/100 EPAMs, the gigabit ports do not come up. This problem has been documented in DDTS CSCdm20899.
Read/write hardware errors occur on Catalyst 8540s with 8-port gigabit and 16-port 10/100 line cards installed. This problem has been documented in DDTS CSCdm25585.
If you are a registered CCO user and you have logged in, you can view the bug details.
Also, the Gigabit Ethernet phyiscal link bounced from "up" to "down" and then "up" again on an interface with Hot Standby Routing Protocol (HSRP) running. The show int command came back with "up up" even though the physical link had shown "down."
Bus errors can occur even without the Gigabit Ethernet combination. The problem can manifest itself in different ways. For example, certain Cisco IOS Software commands have no affect and some IPCs from RP to the line cards would be wrong.
If a second RP is inserted, cells can get stuck in the switching fabric.
If you are a registered CCO user and you have logged in, you can upgrade the FPGA image to fi-c8540-epam.A.3-3. This image can be downloaded from the Cisco Catalyst 8540c FPGA Software page. If you are registered CCO user and you have logged in, you can upgrade the FPGA image to fi-c8540-epam.A.3-3. This image can be downloaded from the Cisco Catalyst 8540c FPGA Software (registered customers only) page.
This image can be downloaded from the Cisco Catalyst 8540c FPGA Software page. This image must be installed on all 10/100 and 100FX EPAMs whose FPGA image revision is earlier than fi-c8540-epam.A.3-3. It is recommended that the FPGA version be upgraded on any chassis where fast Ethernet modules are present.
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