Cisco MGX 8230 Edge Concentrator Overview
Processor Switch Module (PXM1)

Table Of Contents

Processor Switch Module


PXM1 Switch Fabric Module

PXM1 Front Card Support

PXM1 Back Card Support


PXM-UI-S3 (optional)

Uplink Back Cards


Cell Bus Access

Processor (IDT 4700)

Clocking Options


System Environment Monitoring

Alarm Circuit and Indicators

Optical Interfaces

Physical Layer T3/E3 Interface

Physical Layer OC-3c/STM-1 Interface

Physical Layer OC-12c/STM-4 Interface

ATM Layer

Processor Switch Module


The Processor Switch Module (PXM1) provides the switching fabric in the MGX 8230 chassis. This PXM1 allows Cisco customers to scale the switch focus and capacity to 1.2 GBps (PXM1). The PXM1 combines the functions of the processor, the switch fabric, and broadband ports into a single module.

The MGX 8230 supports both shared memory and cross-point switching technologies to optimize costs for narrowband requirements. Although the backplane is capable of 45 GBps, the customer can choose to deploy a 1.2 GBps-shared memory fabric (PXM1) to support the narrowband service modules. The PXM1 provides 1.2 GBps of nonblocking bandwidth.

PXM1 Switch Fabric Module

The switch fabric (PXM1) provides up to 1.2 GBps of nonblocking ATM switching along with an integrated hard disk for statistical and management features and an ATM multicast engine. Figure 3-1 shows the PXM1 architecture.

Figure 3-1 PXM1 Architecture

In addition to the switch processor and switch fabric, the PXM1 module also supports three types of trunking daughter cards, reducing the requirement for allocating additional slot positions for trunk modules. The PXM1 trunking daughter cards and associated back cards are intended to provide native ATM interfaces, which can be configured as either trunks or ports, but are cost-optimized for trunking. The PXM1 trunking back cards are available in the following physical interfaces:

2-port T3/E3 ATM

4-port OC-3c/STM-1 ATM

1-port OC-12c/STM-4 ATM

The PXM1 performs the following functions:

Shelf Management

The PXM1 is responsible for monitoring and controlling the card modules.

Switches Cells

The PXM1 houses the shared-memory switch that sends and receives ATM cells from the network trunk and service modules.

Bus Master

All ATM cells created by the service modules are sent to the PXM1 card to be switched to other service modules or the attached ATM network. The PXM1 is responsible for managing the flow of cells on the cell bus.

Network Management

Network management devices, such as Cisco WAN Manger workstation, PC, and dumb terminal communicate directly with the PXM1

Stores Service Modules Configuration and Firmware Images

A copy of the configuration database and firmware image for each service module installed is stored on the PXM1 on a PCM-CIA disk drive.

Shelf Timing

The PXM1 is responsible for extracting a clock signal from either an external clock source or the trunk to the ATM network. The PXM1 propagates the timing signals across the switch's timing bus.

Measures Environmental Alarms

Chassis temperature and fan and power supply status are monitored by the PXM1.

Local Alarm Notification

Local major and minor alarms are reported by the PXM1 via front card LEDs and dry contact relays on the PXM1-UI back card.

The PXM1 and all the inputs (cell bus and trunk interfaces) support configuration for 1:1 hot-standby redundancy. Each PXM1 supports two active back cards, the upper level back card provides the BITS synchronization interfaces and the OAM interfaces while the lower back card provides the trunk interfaces. Both the active and redundant PXM1 are able to access either pair of the PXM1 back cards, which eliminates the necessity of a PXM1 switch-over if either of the back cards should fail. The
MGX 8230 midplane supports full OC-12c bandwidth to each trunk back card. The PXM1 trunk back cards also support cross-coupling between trunk interfaces for SONET APS 1+1 redundancy support.

All local connections go through QE0 and each local connection consumes two GLCNs (one for each direction). QE0 supports 32K GLCNs so a total of 16K local connections can be supported in hardware.

From a hardware perspective the PXM1 can support up to 32K connections.

PXM1 Front Card Support

The following set of functionality is supported on the PXM1 front card:

+500MB hard drive

High-speed SAR interface into the fabric

Cell bus control and arbitration

Multicast engine

PXM1 Back Card Support

PXM1 back cards provide high-speed (T3, OC-3, OC-12) native ATM interfaces that can be configured as ATM UNI ports or trunks. The interfaces are cost-optimized for trunking. Cross-coupling signals are provided between the lower back cards to allow Automatic Protection Switching (APS). The PXM1 supports two back cards. The upper card supports the following ports and interfaces.

User and Management Interface

EIA/TIA-232 control port

EIA/TIA-232 maintenance port

10BaseT Ethernet port

Network synchronization for the shelf

T1/E1 BITS synchronization port

Stratum-4E clocking

Stratum-3 clocking (optional)

Central office-compatible major/minor alarm interface

DB-15 connector

Major Alarm Audio

Major Alarm Visual

Minor Alarm Visual

The lower back card on PXM1 provide one of the following ATM interfaces:

Two-port T3/E3

Four-port OC-3c/STM-1

One-port OC-12/STM-4

The PXM1 back cards provide user accessible interfaces for the uplink trunks and for management and alarm interfaces.


The PXM1-UI back card provides user access to the following interfaces:

Ethernet port

RS232 maintenance port

RS232 control port

T1/E1 timing reference ports

Audio and visual alarm interface port

PXM-UI-S3 (optional)

The PXM-UI-S3 is an optional card that provides external Stratum 3 clocking. This back card provides user access to the following interfaces:

Ethernet port

RS232 Maintenance port

RS232 Control port

External T1/E1 timing reference ports

Audio and visual alarm interface port

Uplink Back Cards

The uplink back cards provide line drivers for the uplink interface. The following interfaces are provided:

2 T3 ports, BNC connectors

2 E3 ports, BNC connectors

4 OC-3 multimode port, SC connectors

4 OC-3 single mode intermediate reach ports, SC connectors

4 OC-3 single mode long reach ports, SC connectors

1 OC-12 single mode intermediate reach port, SC connectors

1 OC-12 single mode long reach port, SC connectors

A mismatch between the uplink back card type and the PXM1 will generate a major alarm.

Table 3-1 lists the PXM1 modules. Table 3-2 provides the interface characteristics.

Table 3-1 Cisco MGX 8230 Processor Switch Modules 

Front Card


T3/E3 ports


4 155 Mbps ports


1 622 Mbps port


PXM1 user interface BC-PXM1


PXM1 user interface BC-Stratum 3, PXM1, PXM45


2-port E3 back card, BNC connectors


2-port T3 back card, BNC connectors


4-port 155 Mbps back card, MMF, SC connectors


4-port 155 Mbps back card, SMF-IR, SC connectors


4-port 155 Mbps back card, SMF-LR, SC connectors


1 port 622-Mbps back card, SMF-IR, FC connectors


1 port 622-Mbps back card, SMF-LR, FC connectors

Table 3-2 Interface Physical Characteristics 

T3 (DS3)
E3 (34 Mbps)

Line Rate

44.736 Mbps, 20 ppm

34.368 Mbps, 20 ppm

Line Code



Cell Transfer Rate

96,000 cells/sec

80,000 cells/sec


ANSI T1.107, T1.107a

ITU-T G.804, G.832

Signal Level








Cell Mapping

PLLP, Direct

PLLP, Direct


The PXM1 provides 1.2 GBps of nonblocking bandwidth.

Cell Bus Access

The cell bus is a Poll-Request-Grant bus. The polling algorithm is based on round-robin servicing. The granting is based on a programmable rate factor for the device. For example, if a device (service module) has been guaranteed 45 Mbps bandwidth, whenever the grant rate of that device falls below the rate, the priority of the device will be increased until minimum rate is guaranteed.

The eight cell buses are grouped into two groups. Excess bandwidth is proportionally shared among all devices within the same group.

When the cell buses are running at double speed, each cell bus is guaranteed 160 Mbps bandwidth. The excess bandwidth is shared proportionally among all devices within the same group. Therefore it is important that one does not attempt to set the total guaranteed bandwidth for either the left side or right side of the chassis to be more than 640 Mbps.

Processor (IDT 4700)

The IDT 4700 processor module provides the following basic features:

Clock Speed - 200 MHz internal, 50 MHz external

Flash—2 MB


Secondary Cache—512 KB


Clocking Options

The PXM1 supports a minimum of two external timing references on separate physical interfaces. These are provisioned as the active (act) and alternate (alt). The terms act and alt are interchangeable depending on which reference is active, and providing timing reference for the system. The system also provides a DS1 reference for external timing in D4 (SF) format. At least two DS1 synchronization references, as specified in Bellcore GR-1244-CORE, Section 3.4, can be configured.

A switchover from the active clock source (primary or secondary) to the standby clock source will occur when the hardware detects a failure that warrants a switchover. The currently selected clock source is constantly monitored by the hardware to ensure that it is within tolerance.

If a failure in this selected clock is detected, the hardware gracefully switches over to the secondary clock source specified.

If both the primary and secondary sources have failed, the hardware will automatically output the clock generated internally on the card. Once the primary clock is within tolerance, the hardware will automatically switch back to it.

Regardless of whether the clock switchover is initiated by the user or by the hardware, the switchover meets the Accunet T1.5 Maximum Time Interval Error (MTIE) specification.

When all timing references fail, as specified in Bellcore GR-1244-CORE, Section 3.4.1, the MGX 8230 can operate in self-timing, or free-running mode, using an internal clock.


The user interface back card features are as follows.

Resides in the upper service bay

Interfaces supported

T1/E1 timing reference ports

Maintenance port

Control port

Ethernet interface

Audio and visual alarm interface ports

Y-Cable support available

System Environment Monitoring

The following system environmental parameters are monitored and logged by the PXM1:

48 VAC power supply status

5V and 3.3V on-board power status

Cooling fan revolution

Enclosure temperature

Minor and major alarms will be generated when one or more environmental parameters are out of range.

Alarm Circuit and Indicators

PXM1 provides connectors for external audio and visual alarms. The PXM1 monitors ACO and History push-buttons located in its front card faceplate. It controls the following LEDs, which are also located on the PXM1 front card faceplate:


Active (green)

Standby (yellow)

Fail (red)

LAN activity

Flashing green

Node alarm

Major alarm (red)

Minor alarm (yellow)

Node Power Supply

DC OK A (green/red)

DC OK B (green/red)

Alarm History



Port Interface (per port):

Active and OK (green)

Active and local alarm (red)

Active and remote alarm (yellow)

Inactive (no light)

Figure 3-2 shows the PXM1 LEDs.

Figure 3-2 PXM1 LEDs

PXM1 provides three types of nonvolatile storage:

Flash—This is used to store boot code for the processor. The boot code can be upgraded in the field by a software download.

Hard drive—The PXM1 hard drive is a 2.5 inch, 2.2 GB IDE drive. Configuration information and code for the PXM1 and service modules are stored on the drive, and can be updated during system operation or by user download.

Battery backed up RAM—The BRAM is used to store book keeping information for the card. Information stored includes:

Identifiers such as board hardware revision, serial number, and PCB part number

MAC address of the PXM1

Hard drive parameters such as number of heads and cylinder size

The BRAM also acts as a temporary cache. If for any reason the hard drive fails, log information immediately before the failure can be stored in the BRAM for further analysis.

Optical Interfaces

As the optical transceivers in the PXM1 interfaces are ITU-T G.957 compiant, G.957 dispersion tolerances are:

STM-1 Intermediate Reach (S-1.1)

Maximum dispersion in the optical path is 96 ps/nm

STM-1 Long Reach (L-1.1)

Maximum dispersion in the optical path is 185 ps/nm

STM-4 Intermediate Reach (S-4.1)

Maximum dispersion in the optical path is 74 ps/nm

STM-4 Long Reach (L-4.1)

Maximum dispersion in the optical path is 109 ps/nm

The modulation used in all PXM1 optics is direct built-in electroabsortion modulator in standard temperature range (0-70°C). The type of laser sources for the different PXM1 interfaces are

OC-3 IR: Fabry-Perot

OC-3 LR: Fabry-Perot

OC-12 IR: Fabry-Perot


Physical Layer T3/E3 Interface

The T3/E3 interface provides

Two T3/E3 ports

Compliance with ATM Forum UNI Specification Versions 3.0 and 3.1

1:1 PXM1 redundancy

Both PLCP and HEC direct mapping for T3; HEC direct mapping for E3

Physical Layer OC-3c/STM-1 Interface

The OC-3c/STM-1 interface provides

Four OC-3c/STM-1 (155.520 Mbps) ports

Trunk or port interface mode

Cell transfer rate of 353,208 cells per second

Compliance with SONET standards (Bellcore GR-253-CORE and ANSI T1.105)

Compliance with SDH standards (ITU-T G.707, G.708, G.709, G.957, and G.958)

1:1 PXM1 redundancy


Linear APS

Physical Layer OC-12c/STM-4 Interface

The OC-12c/STM-4 interface provides:

One OC-12c/STM-4 (622.08 Mbps) port

Cell transfer rate of 1,412,832 cells per second

Compliance with SONET standards (Bellcore GR-253-CORE, TR-TSY-000020, ANSI T1.105)

Compliance with SDH standards (ITU-T G.707, G.708, G.709, G.957, G.958)

1:1 PXM1 redundancy


ATM Layer

The ATM layer is configurable for trunk and public or private UNI applications. It is conformant to ATM Forum UNI Specification V3.0, 3.1, ITU-T I.361 and I.432 specifications, and it supports virtual circuit connections (VCCs) and virtual path connections (VPCs) per ATM Forum UNI Specification V3.1 and ITU-T I.371.