Table Of Contents

Overview of the Gigabit Ethernet SPAs

Release History

Supported Features

Supported MIBs

SPA Architecture

Path of a Packet in the Ingress Direction

Path of a Packet in the Egress Direction

Displaying the SPA Hardware Type

Example of the show interfaces Command

Overview of the Gigabit Ethernet SPAs

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This chapter provides an overview of the release history, and feature and Management Information Base (MIB) support for the Gigabit Ethernet SPAs on the Cisco ASR 1000 Series Aggregation Services Routers.

This chapter includes the following sections:

•Release History

•Supported Features

•Supported MIBs

•SPA Architecture

•Displaying the SPA Hardware Type

Release History

 

Release

Modification

Cisco IOS XE Release 2.1

First release. Support for the following SPAs was introduced on the Cisco ASR1000-SIP10 on the Cisco ASR 1000 Series Routers: Fast Ethernet SPAs •4-Port Fast Ethernet SPA—SPA-4X1FE-TX-V2 •8-Port Fast Ethernet SPA—SPA-8X1FE-TX-V2 Gigabit Ethernet SPAs •10-Port Gigabit Ethernet SPA, Version 2—SPA-10X1GE-V2 •8-Port Gigabit Ethernet SPA, Version 2—SPA-8X1GE-V2 •5-Port Gigabit Ethernet SPA, Version 2—SPA-5X1GE-V2 •2-Port Gigabit Ethernet SPA, Version 2— SPA-2X1GE-V2 •1-Port 10-Gigabit Ethernet SPA, Version 2—SPA-1X10GE-L-V2

Supported Features

The following is a list of some of the significant hardware and software features supported by Gigabit Ethernet SPAs on the Cisco ASR 1000 Series Routers:

•Autonegotiation

•Auto-MDI/MDIX detection (Fast Ethernet and 2-Port Gigabit Ethernet SPAs only)

•Full-duplex operation

•802.1Q VLAN termination

•Jumbo frames support (9216 bytes)

•Support for command-line interface (CLI)-controlled OIR

•802.3x flow control

•Up to 8000 VLANs per SPA

•Up to 5000 MAC Accounting Entries per SPA (Source MAC Accounting on the ingress and Destination MAC Accounting on the egress)

•Per-port byte and packet counters for policy drops, oversubscription drops, CRC error drops, packet sizes, unicast, multicast, and broadcast packets

•Per-VLAN byte and packet counters for policy drops, oversubscription drops, unicast, multicast, and broadcast packets

•Per-port byte counters for good bytes and dropped bytes

•Multiprotocol Label Switching (MPLS)

•Quality of Service (QoS)

•Hot Standby Router Protocol (HSRP)

Supported MIBs

The following MIBs are supported by the Gigabit Ethernet SPAs on the Cisco ASR 1000 Series Routers:

•ENTITY-MIB (RFC 4133)

•CISCO-ENTITY-FRU-CONTROL-MIB

•CISCO-ENTITY-ALARM-MIB

•ENTITY-SENSOR-MIB (RFC 3433)

•CISCO-ENTITY-SENSOR-MIB

•IF-MIB

•ETHERLIKE-MIB (RFC 3635)

•Remote Monitoring (RMON)-MIB (RFC 1757)

•CISCO-CLASS-BASED-QOS-MIB

•MPLS-related MIBs

To locate and download MIBs for selected platforms, Cisco IOS releases, and feature sets, use Cisco MIB Locator found at the following URL:

http://tools.cisco.com/ITDIT/MIBS/servlet/index

If Cisco MIB Locator does not support the MIB information that you need, you can also obtain a list of supported MIBs and download MIBs from the Cisco MIBs page at the following URL:

http://www.cisco.com/public/sw-center/netmgmt/cmtk/mibs.shtml

To access Cisco MIB Locator, you must have an account on Cisco.com. If you have forgotten or lost your account information, send a blank e-mail to cco-locksmith@cisco.com. An automatic check will verify that your e-mail address is registered with Cisco.com. If the check is successful, account details with a new random password will be e-mailed to you. Qualified users can establish an account on Cisco.com by following the directions found at this URL:

http://www.cisco.com/register

SPA Architecture

This section provides an overview of the architecture of the Gigabit Ethernet SPAs and describes the path of a packet in the ingress and egress directions. Some of these areas of the architecture are referenced in the SPA software and can be helpful to understand when troubleshooting or interpreting some of the SPA CLI and show command output.

Every incoming and outgoing packet on the Gigabit Ethernet SPAs goes through the physical (PHY) SFP optics, the Media Access Controller (MAC), and a Layer 2 Filtering/Accounting ASIC.

Path of a Packet in the Ingress Direction

The following steps describe the path of an ingress packet through the Gigabit Ethernet SPAs:

1. For one-Gigabit Ethernet SPAs, the SFP optics receive incoming frames on a per-port basis from one of the optical fiber interface connectors.

2. For ten-Gigabit Ethernet SPAs, the XFP PHY device processes the frame and sends it over a serial interface to the MAC device.

3. The MAC device receives the frame, strips the CRCs, and sends the packet via the SPI 4.2 bus to the ASIC.

4. The ASIC takes the packet from the MAC devices and classifies the Ethernet information. CAM lookups based on Ethertype, port, VLAN, and source and destination address information determine whether the packet is dropped or forwarded to the SPA interface.

Path of a Packet in the Egress Direction

The following steps describe the path of an egress packet from the SIP through the Gigabit Ethernet SPAs:

1. The packet is sent to the ASIC using the SPI 4.2 bus. The packets are received with Layer 2 and Layer 3 headers in addition to the packet data.

2. The ASIC uses port number, destination MAC address, destination address type, and VLAN ID to perform parallel CAM lookups. If the packet is forwarded, it is forwarded via the SPI 4.2 bus to the MAC device.

3. For Gigabit Ethernet SPAs, the MAC device forwards the packets to the PHY laser-optic interface, which transmits the packet.

Displaying the SPA Hardware Type

To verify the SPA hardware type that is installed in your Cisco ASR 1000 Series Routers, you can use the show platform command.

Table 9-1 shows the hardware description that appears in the show interfaces command output for each Gigabit Ethernet SPA that is supported on the Cisco ASR 1000 Series Routers.

Table 9-1 SPA Hardware Descriptions in show Commands

SPA	Description in show interfaces Command
4-Port Fast Ethernet SPA	Hardware is SPA-4X1FE-TX-V2
8-Port Fast Ethernet SPA	Hardware is SPA-8X1FE-TX-V2
10-Port Gigabit Ethernet SPA	Hardware is SPA-10X1GE-V2
8-Port Gigabit Ethernet SPA	Hardware is SPA-8X1GE-v2
5-Port Gigabit Ethernet SPA	Hardware is SPA-5X1GE-V2
2-Port Gigabit Ethernet SPA	Hardware is SPA-2X1GE-V2
1-Port 10-Gigabit Ethernet SPA	Hardware is SPA-1X10GE-L-V2

Example of the show interfaces Command

The following example shows output from the show interfaces tengigabitethernet command on a Cisco ASR 1000 Series Routers with a 1-Port 10-Gigabit Ethernet SPA installed in slot 7:

Router# show interfaces tengigabitethernet7/0/0

  TenGigabitEthernet0/0/0 is up, line protocol is up (connected)

  Hardware is SPA-1X10GE-L-V2, address is 0000.0c00.0102 (bia 000f.342f.c340)

  Internet address is 15.1.1.2/24

  MTU 1500 bytes, BW 10000000 Kbit, DLY 10 usec, 

     reliability 255/255, txload 1/255, rxload 1/255

  Encapsulation ARPA, loopback not set

  Keepalive not supported

  Full-duplex, 10Gb/s

  input flow-control is on, output flow-control is on 

  ARP type: ARPA, ARP Timeout 04:00:00

  Last input never, output 00:00:10, output hang never

  Last clearing of "show interface" counters 20:24:30

  Input queue: 0/75/0/0 (size/max/drops/flushes); Total output drops: 0

  Queueing strategy: fifo

  Output queue: 0/40 (size/max)

  5 minute input rate 0 bits/sec, 0 packets/sec

  5 minute output rate 0 bits/sec, 0 packets/sec

  L2 Switched: ucast: 0 pkt, 0 bytes - mcast: 0 pkt, 0 bytes

  L3 in Switched: ucast: 0 pkt, 0 bytes - mcast: 0 pkt, 0 bytes mcast

  L3 out Switched: ucast: 0 pkt, 0 bytes mcast: 0 pkt, 0 bytes

     237450882 packets input, 15340005588 bytes, 0 no buffer

     Received 25 broadcasts (0 IP multicasts)

     0 runts, 0 giants, 0 throttles

     0 input errors, 0 CRC, 0 frame, 0 overrun, 0 ignored

     0 watchdog, 0 multicast, 0 pause input

     0 input packets with dribble condition detected

     1676 packets output, 198290 bytes, 0 underruns

     0 output errors, 0 collisions, 4 interface resets

     0 babbles, 0 late collision, 0 deferred

     0 lost carrier, 0 no carrier, 0 PAUSE output

     0 output buffer failures, 0 output buffers swapped out