Table Of Contents
Overview of the ATM SPAs
Release History
Supported Features
Basic Features
SONET/SDH Error, Alarm, and Performance Monitoring
Layer 2 Features
Layer 3 Features
High Availability Features
Restrictions
Supported MIBs
SPA Architecture
Path of Cells in the Ingress Direction
Path of Packets in the Egress Direction
Displaying the SPA Hardware Type
Example of the show interfaces Command
Example of the show controllers Command
Overview of the ATM SPAs
This chapter provides an overview of the release history, features, and MIB support for the 1-Port OC-3 ATM SPA and the 3-Port OC-3 ATM SPA. This chapter includes the following sections:
•
Release History
•Supported Features
•Restrictions
•Supported MIBs
•SPA Architecture
•Displaying the SPA Hardware Type
Release History
Release
|
Modification
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IOS XE 2.3
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Initial release for the 1-Port OC-3 ATM SPA and 3-Port OC-3 ATM SPA for Cisco ASR 1000 Series Routers.
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Supported Features
This section provides a list of some of the primary features supported by the ATM hardware and software:
•Basic Features
•SONET/SDH Error, Alarm, and Performance Monitoring
•Layer 2 Features
•Layer 3 Features
•High Availability Features
Basic Features
•Bellcore GR-253-CORE SONET/SDH compliance (ITU-T G.707, G.783, G.957, G.958)
•Interface-compatible with other Cisco ATM adapters
Note The ATM SPA is functionally similar to other ATM port adapters on the Cisco ASR 1000 Series Routers, but because it is a different card type, the configuration for the slot is lost when you replace an existing ATM port adapter with an ATM SPA in a SIP.
•Supports permanent virtual circuits (PVCs).
•RFC 2684: Routed PVCs (snap/mux) (formerly RFC 1483).
•An absolute maximum of 1,000 (1K) configured VCs per ATM SPA (1,000 [1K] per interface) with the following recommended limitations:
–A recommended maximum number of 1,000 PVCs on all point-to-point subinterfaces for all ATM SPAs in a SIP.
–A recommended maximum number of 1,000 PVCs on all multipoint subinterfaces for all ATM SPAs in a SIP, and a recommended maximum number of 1 PVC per each individual multipoint subinterface.
–A recommended maximum number of 1,024 PVCs using service policies for all ATM SPAs in a SIP.
•Up to 4,096 simultaneous segmentations and reassemblies (SARs) per interface
•A maximum number of 4,000 PVCs configured with Modular QoS CLI (MQC) policy maps
•ATM adaptation layer 5 (AAL5) for data traffic
•Uses small form-factor pluggable (SFP) optical transceivers, allowing the same ATM SPA hardware to support multimode (MM), single-mode intermediate (SMI), or single-mode long (SML) reach, depending on the capabilities of the SPA
•ATM section, line, and path alarm indication signal (AIS) cells, including support for F4 and F5 flows, loopback, and remote defect indication (RDI)
•Operation, Administration, and Maintenance (OAM) cells
•Online insertion and removal (OIR) of individual ATM SPAs from the SIP, as well as OIR of the SIPs with ATM SPAs installed
SONET/SDH Error, Alarm, and Performance Monitoring
•Fiber removed and reinserted
•Signal failure bit error rate (SF-BER)
•Signal degrade bit error rate (SD-BER)
•Signal label payload construction (C2)
•Path trace byte (J1)
•Section Diagnostics:
–Loss of signal (SLOS)
–Loss of frame (SLOF)
–Error counts for B1
–Threshold crossing alarms (TCA) for B1 (B1-TCA)
•Line Diagnostics:
–Line alarm indication signal (LAIS)
–Line remote defect indication (LRDI)
–Line remote error indication (LREI)
–Error counts for B2
–Threshold crossing alarms for B2 (B2-TCA)
•Path Diagnostics:
–Path alarm indication signal (PAIS)
–Path remote defect indication (PRDI)
–Path remote error indication (PREI)
–Error counts for B3
–Threshold crossing alarms for B3 (B3-TCA)
–Loss of pointer (PLOP)
–New pointer events (NEWPTR)
–Positive stuffing event (PSE)
–Negative stuffing event (NSE)
•The following loopback tests are supported:
–Network (line) loopback
–Internal (diagnostic) loopback
•Supported SONET/SDH synchronization:
–Local (internal) timing (for inter-router connections over dark fiber or wavelength division multiplexing [WDM] equipment)
–Loop (line) timing (for connecting to SONET/SDH equipment)
–+/- 4.6 ppm clock accuracy over full operating temperature
Layer 2 Features
•Supports the following encapsulation types:
–AAL5SNAP (LLC/SNAP)
–AAL5MUX (VC multiplexing)
•Supports the following ATM traffic classes and per-VC traffic shaping modes:
–Constant bit rate (CBR) with peak rate
–Unspecified bit rate (UBR) with peak cell rate (PCR)
–Non-real-time variable bit rate (VBR-nrt)
–Variable bit rate real-time (VBR-rt)
Note ATM shaping is supported, but class queue-based shaping is not.
•ATM point-to-point and multipoint connections
•Explicit Forward Congestion Indication (EFCI) bit in the ATM cell header
•AToM VP and VC Mode Cell Relay support
•RFC 2225, Classical IP and ARP over ATM (obsoletes RFC 1577)
Layer 3 Features
•ATM over MPLS (AToM) in AAL0 VC and VP mode
•No limitation on the maximum number of VCs per VPI, up to the maximum number of 4,096 total VCs per interface (so there is no need to configure this limit using the atm vc-per-vp command, which is required on other ATM SPAs)
•OAM flow connectivity using OAM ping for segment or end-to-end loopback
•PVC multicast (Protocol Independent Multicast [PIM] dense and sparse modes)
•Supports oversubscription by default
•Routing protocols:
–Border Gateway Protocol (BGP)
–Enhanced Interior Gateway Routing Protocol (EIGRP)
–Interior Gateway Routing Protocol (IGRP)
–Integrated Intermediate System-to-Intermediate System (IS-IS)
–Open Shortest Path First (OSPF)
–Routing Information Protocol version 1 and version 2 (RIPv1 and RIPv2)
High Availability Features
•Route Processor Redundancy (RPR)
•OSPF Nonstop Forwarding (NSF)
•Stateful Switchover (SSO)
Restrictions
•The ATM SPAs in the Cisco ASR 1000 Series Routers do not support APS reflector and reflector channel modes. (These modes require a facing path terminating element [PTE], which is typically a Cisco ATM switch.)
•For best performance, we recommend the following maximums:
–A maximum number of 1,000 PVCs on all point-to-point subinterfaces for all ATM SPAs in a SIP.
–A maximum number of 1,000 PVCs on all multipoint subinterfaces for all ATM SPAs in a SIP.
–A maximum number of 1024 PVCs using service policies for all ATM SPAs in a router.
–A maximum number of 1 PVC on each multipoint subinterface being used on an ATM SPA.
Note These limits are flexible and depend on all factors that affect performance in the router, such as processor card, type of traffic, and so on.
•In the default configuration of the transmit path trace buffer, the ATM SPA does not support automatic updates of remote host name and IP address (as displayed by the show controllers atm command). This information is updated only when the interface is shut down and reactivated (using the shutdown and no shutdown commands). Information for the received path trace buffer, however, is automatically updated.
Supported MIBs
The following MIBs are supported in Cisco IOS XE Release 2.3 and later releases for the ATM SPAs on the Cisco ASR 1000 Series Routers.
Common MIBs
•ENTITY-MIB
•IF-MIB
•MIB-II
•MPLS-CEM-MIB
Cisco-Specific Common MIBs
•CISCO-ENTITY-EXT-MIB
•OLD-CISCO-CHASSIS-MIB
•CISCO-CLASS-BASED-QOS-MIB
•CISCO-ENTITY-FRU-CONTROL-MIB
•CISCO-ENTITY-ASSET-MIB
•CISCO-ENTITY-SENSOR-MIB
•CISCO-MQC-MIB
Cisco-Specific MPLS MIBs
•CISCO-IETF-PW-MIB
•CISCO-IETF-PW-MPLS-MIB
For more information about MIB support on a Cisco ASR 1000 Series Routers, refer to the Cisco ASR 1000 Series Aggregation Services Routers MIB Specifications Guide, at the following URL:
http://www.cisco.com/en/US/docs/routers/asr1000/mib/guide/asr1kmib.html
To locate and download MIBs for selected platforms, Cisco IOS releases, and feature sets, use Cisco MIB Locator found at the following URL:
http://tools.cisco.com/ITDIT/MIBS/servlet/index
If Cisco MIB Locator does not support the MIB information that you need, you can also obtain a list of supported MIBs and download MIBs from the Cisco MIBs page at the following URL:
http://www.cisco.com/public/sw-center/netmgmt/cmtk/mibs.shtml
To access Cisco MIB Locator, you must have an account on Cisco.com. If you have forgotten or lost your account information, send a blank e-mail to cco-locksmith@cisco.com. An automatic check will verify that your e-mail address is registered with Cisco.com. If the check is successful, account details with a new random password will be e-mailed to you. Qualified users can establish an account on Cisco.com by following the directions found at this URL:
http://www.cisco.com/register
SPA Architecture
This section provides an overview of the data path for the ATM SPAs, for use in troubleshooting and monitoring. Figure 6-1 shows the data path for ATM traffic as it travels between the ATM optical connectors on the front panel of the ATM SPA to the backplane connector that connects the SPA to the SIP.
Figure 6-1 ATM SPA Data Architecture
Path of Cells in the Ingress Direction
The following steps describe the path of an ingress cell as it is received from the ATM network and converted to a data packet before transmission through the SIP to the router's processors for switching, routing, or further processing:
1. The SONET/SDH framer device receives incoming cells on a per-port basis from the SPA's optical circuitry. (The ATM SPA supports 1 or 3 optical ports, depending on the model of SPA.)
2. The SONET/SDH framer removes the SONET overhead information, performs any necessary clock and data recovery, and processes any SONET/SDH alarms that might be present. The framer then extracts the 53-byte ATM cells from the data stream and forwards each cell to the ATM segmentation and reassembly (SAR) engine.
3. The SAR engine receives the cells from the framer and reassembles them into the original packets, temporarily storing them in a per-port receive buffer until they can be forwarded to the LFI field-programmable gate array (FPGA). The SAR engine discards any packets that have been corrupted in transit.
4. The LFI FPGA receives the packets from the SAR engine and forwards them to the host processor for further routing, switching, or additional processing. The FPGA also performs LFI reassembly as needed, and collects the traffic statistics for the packets that it passes.
Path of Packets in the Egress Direction
The following steps describe the path of an egress packet as the SPA receives it from the router through the SIP and converts it to ATM cells for transmission on the ATM network:
1. The LFI FPGA receives the packets from the host processor and stores them in its packet buffers until the SAR engine is ready to receive them. The FPGA also performs any necessary LFI processing on the packets before forwarding them to the SAR engine. The FPGA also collects the traffic statistics for the packets that it passes.
2. The SAR engine receives the packets from the FPGA and supports multiple CBWFQ queues to store the packets until they can be fully segmented. The SAR engine performs the necessary WRED queue admission and CBWFQ QoS traffic scheduling on its queues before segmenting the packets into ATM cells and shaping the cells into the SONET/SDH framer.
3. The SONET/SDH framer receives the packets from the SAR engine and inserts each cell into the SONET data stream, adding the necessary clocking, SONET overhead, and alarm information. The framer then outputs the data stream out the appropriate optical port.
4. The optical port conveys the optical data onto the physical layer of the ATM network.
Displaying the SPA Hardware Type
To verify the SPA hardware type that is installed in your Cisco ASR 1000 Series Routers, use the show interfaces, or show controllers commands. A number of other show commands also provide information about the SPA hardware.
Table 6-1 shows the hardware description that appears in the show interfaces command output for each ATM SPA that is supported on the Cisco ASR 1000 Series Routers:
Table 6-1 ATM SPA Hardware Descriptions in show interfaces Command
SPA
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Description in show interfaces Command
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SPA-1XOC3-ATM-V2
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"Hardware is SPA-1XOC3-ATM"
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SPA-3XOC3-ATM-V2
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"Hardware is SPA-3XOC3-ATM"
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Example of the show interfaces Command
The following example shows output from the show interfaces atm command on a Cisco ASR 1000 Series Routers with an ATM SPA installed in the second subslot of a SIP that is installed in slot 0:
Router#show interfaces atm 0/2/2
ATM0/2/2 is up, line protocol is up
Hardware is SPA-3XOC3-ATM-V2, address is 001a.3044.7522 (bia 001a.3044.7522)
MTU 4470 bytes, sub MTU 4470, BW 149760 Kbit, DLY 80 usec,
reliability 255/255, txload 1/255, rxload 1/255
Encapsulation ATM, loopback not set
Encapsulation(s): AAL5 AAL0
4095 maximum active VCs, 1 current VCCs
VC Auto Creation Disabled.
VC idle disconnect time: 300 seconds
Last input never, output 00:04:11, output hang never
Last clearing of "show interface" counters never
Input queue: 0/375/0/0 (size/max/drops/flushes); Total output drops: 0
Output queue: 0/40 (size/max)
5 minute input rate 0 bits/sec, 0 packets/sec
5 minute output rate 0 bits/sec, 0 packets/sec
5 packets input, 540 bytes, 0 no buffer
Received 0 broadcasts (0 IP multicasts)
0 runts, 0 giants, 0 throttles
0 input errors, 0 CRC, 0 frame, 0 overrun, 0 ignored, 0 abort
5 packets output, 540 bytes, 0 underruns
0 output errors, 0 collisions, 1 interface resets
0 output buffer failures, 0 output buffers swapped out
Example of the show controllers Command
The following example shows output from the show controllers atm command on a Cisco ASR 1000 Series Routers with an ATM SPA installed in the second subslot of a SIP that is installed in slot 0:
Router# show controllers atm 0/2/2
Interface ATM0/2/2 (SPA-3XOC3-ATM-V2[0/2]) is up
Framing mode: SONET OC3 STS-3c
LOF = 0 LOS = 1 BIP(B1) = 0
AIS = 0 RDI = 1 FEBE = 55 BIP(B2) = 0
AIS = 0 RDI = 1 FEBE = 21 BIP(B3) = 0
LOP = 1 NEWPTR = 0 PSE = 0 NSE = 0
Alarm reporting enabled for: SF SLOS SLOF B1-TCA B2-TCA PLOP B3-TCA
State: PSBF_state = False
Rx(K1/K2): 00/00 Tx(K1/K2): 00/00
Rx Synchronization Status S1 = 00
PATH TRACE BUFFER : STABLE
BER thresholds: SF = 10e-3 SD = 10e-6
TCA thresholds: B1 = 10e-6 B2 = 10e-6 B3 = 10e-6
