NPE-100, NPE-150, and NPE-200 Overview
This chapter describes the network processing engine (NPE) models NPE-100, NPE-150, and NPE-200 and contains the following sections:
•Supported Platforms
•Software Requirements
•NPE-100, NPE-150, and NPE-200 Description and Overview
•NPE-100, NPE-150, and NPE-200 Memory Information
Supported Platforms
The following NPEs support the Cisco 7200 series routers and Cisco 7200 VXR routers:
•NPE-100
•NPE-150
•NPE-200
The following NPEs support the Cisco uBR7246 and Cisco uBR7223 universal broadband routers:
•NPE-150
•NPE-200
The NPE-200 supports the Cisco 7206 as a router shelf in a Cisco AS5800 Universal Access Server.
Software Requirements
For minimum software release information, see the "Software Requirements" section on page 8-4.
NPE-100, NPE-150, and NPE-200 Description and Overview
This section contains information about the network processing engine components and the system management functions.
•The network processing engine maintains and executes the system management functions for the Cisco 7200 series routers.
•The network processing engine maintains and executes the system management functions for the Cisco uBR7200 series routers.
The NPE also shares the system memory and environmental monitoring functions with the I/O controller.
Components
Figure 1-1 NPE-100
|
System controller |
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Midplane connectors |
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R4700 microprocessor |
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Temperature sensor |
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Captive installation screw |
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DRAM SIMMs |
|
Handle |
|
Bank 1 |
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Temperature sensor |
|
Bank 0 |
Figure 1-2 NPE-150
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System controller |
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Midplane connectors |
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R4700 microprocessor |
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Temperature sensor |
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1-MB SRAM (U700 through U703 and U800 through U803) |
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DRAM SIMMs |
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Captive installation screw |
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Bank 1 |
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Handle |
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Bank 0 |
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Temperature sensor |
|
|
Figure 1-3 NPE-200
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System controller |
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Midplane connectors |
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R5000 microprocessor |
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Temperature sensor |
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4-MB SRAM (U6, U10, U13, U14, U28, U29, U38, and U39) |
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Boot ROM U92 |
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Captive installation screw |
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DRAM SIMMs |
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Handle |
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Bank 1 |
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Temperature sensor |
|
Bank 0 |
The NPE-100, NPE-150, and NPE-200 consist of the following components:
•Reduced instruction set computing (RISC) microprocessor
–The NPE-100 and NPE-150 have an R4700 microprocessor that operates at an internal clock speed of 150 MHz.
–The NPE-200 has an R5000 microprocessor that operates at an internal clock speed of 200 MHz.
•System controller
The system controller provides hardware logic to interconnect the processor, DRAM, and the PCI-based system backplane bus. The NPE-150 and NPE-200 have a system controller that uses direct memory access (DMA) to transfer data between DRAM and packet SRAM on the network processing engine.
•Upgradable memory modules
The NPE-100, NPE-150, and NPE-200 use DRAM for storing routing tables, network accounting applications, packets of information in preparation for process switching, and packet buffering for SRAM overflow (except in the NPE-100, which contains no packet SRAM). The standard configuration is 32 MB, with up to 128 MB available through single in-line memory module (SIMM) upgrades.
•Packet SRAM for storing data packets
–The NPE-100 does not have packet SRAM.
–The NPE-150 has 1 MB of SRAM.
–The NPE-200 has 4 MB of SRAM.
•Cache memory
The NPE-100, NPE-150, and NPE-200 have unified cache SRAM that functions as the secondary cache for the microprocessor. (The primary cache is within the microprocessor.)
•Two environmental sensors for monitoring the cooling air as it leaves the chassis
•Boot ROM for storing sufficient code for booting the Cisco IOS software on the NPE-200
Note The NPE-100 and NPE-150 use the boot ROM on the I/O controller.
System Management Functions
The network processing engines perform the following system management functions:
•Sending and receiving routing protocol updates
•Managing tables, caches, and buffers
•Monitoring interface and environmental status
•Providing Simple Network Management Protocol (SNMP) management through the console and Telnet interface
•Accounting for and switching of data traffic
•Booting and reloading images
•Managing port adapters (including recognition and initialization during online insertion and removal)
Terms and Acronyms
•Cache—Memory with fast access and small capacity used to temporarily store recently accessed data; found either incorporated into the processor or near it.
•DIMM—dual in-line memory module
•DRAM—dynamic random-access memory
•Instruction and data cache—Instructions to the processor, and data on which the instructions work.
•Integrated cache—Cache that is built into the processor; sometimes referred to as internal cache. Cache memory physically located outside the processor is not integrated, and is sometimes referred to as external cache.
•OTP—one time programmable
•Primary, secondary, tertiary cache—Hierarchical cache memory storage based on the proximity of the cache to the core of the processor. Primary cache is closest to the processor core and has the fastest access. Secondary cache has slower access than primary cache, but faster access than tertiary cache.
•RAM—random-access memory
•RISC—reduced instruction set computing
•ROM—read-only memory
•SIMM—single in-line memory module
•SDRAM—synchronous dynamic random-access memory
•SDRAM-fixed—SDRAM of a fixed size or quantity; can be replaced, but not upgraded
•SODIMM—small outline dual in-line memory module
•SRAM—static random-access memory
•Unified cache—Instruction cache and data cache are combined. For example, a processor may have primary cache with separate instruction and data cache memory, but unified secondary cache.
NPE-100, NPE-150, and NPE-200 Memory Information
To determine the memory configuration of your NPE, use the show version command.
The following example shows an NPE-150 installed in a Cisco 7206 router:
router(boot)# show version
Cisco Internetwork Operating System Software
IOS (tm) 7200 Software (C7200-J-M), Released Version 11.1(17)CA
Copyright (c) 1986-1999 by cisco Systems, Inc.
Compiled Sun 21-Apr-96 04:10
Image text-base:0x60010890, data-base:0x605F0000
cisco 7206 (NPE150) processor with 12288K/4096K bytes of memory.
R4700 processor, Implementation 33, Rev 1.0, (Level 2 Cache)
Last reset from power-on
(display text omitted)
Use the following sections for information about memory specifications and configurations for the NPE-100, NPE-150, and NPE-200.
Note To prevent DRAM errors in the NPE-100, NPE-150, or NPE-200, and to ensure that your system initializes correctly at startup, DRAM bank 0 (socket U18 and U25, or U11 and U25) must contain no fewer than two SIMMs of the same type. You may also install two SIMMs of the same type in bank 1 (socket U4 and U12, or U42 and U52); however, bank 0 must always contain the two largest SIMMs.
NPE-100 Memory Information
Table 1-1 provides information about memory specifications. Table 1-2 provides memory configurations for the NPE-100.
Table 1-1 NPE-100 Memory Specifications
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|
|
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Component Location on the NPE-100 Baord
|
DRAM |
32 to 128 MB |
2 to 4 |
16- or 32-MB SIMMs (based on maximum DRAM required) |
Bank 0: U18 and U25 Bank 1: U4 and U12 |
Primary cache |
— |
— |
R4700 processor, internal cache |
U201 |
Secondary cache |
512 KB |
4 |
R4700 processor, unified, external cache |
U2, U10, U14, and U26 |
Table 1-2 NPE-100 DRAM SIMM Configurations—Configurable Memory Only
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|
|
|
|
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32 MB |
U18 and U25 |
2 16-MB SIMMs2 |
U4 and U12 |
— |
MEM-NPE-32MB2 |
64 MB |
U18 and U25 |
2 32-MB SIMMs |
U4 and U12 |
— |
MEM-NPE-64MB2 |
128 MB |
U18 and U25 |
2 32-MB SIMMs |
U4 and U12 |
2 32-MB SIMMs |
MEM-NPE-128MB2 |
NPE-150 Memory Information
Table 1-3 provides information about memory specifications. Table 1-4 provides memory configurations for the NPE-150.
Table 1-3 NPE-150 Memory Specifications
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|
|
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Component Location on the NPE-150 Board
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DRAM |
32 to 128 MB |
2 to 4 |
16- or 32-MB SIMMs (based on maximum DRAM required) |
Bank 0: U18 and U2 Bank 1: U4 and U12 |
SRAM |
1 MB |
8 |
8 chips, each being 128K x 9 bits wide |
U700 through U703 U800 through U803 |
Primary cache |
— |
— |
R4700 processor, internal cache |
U201 |
Secondary cache |
512 MB |
4 |
R4700 processor, unified, external cache |
U2, U10, U14, and U26 |
Table 1-4 NPE-150 DRAM SIMM Configurations—Configurable Memory Only
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|
|
|
|
|
32 MB |
U18 and U25 |
2 16-MB SIMMs |
U4 and U12 |
— |
MEM-NPE-32 MB2 |
64 MB |
U18 and U25 |
2 32-MB SIMMs |
U4 and U12 |
— |
MEM-NPE-64MB2 |
128 MB |
U18 and U25 |
2 32-MB SIMMs |
U4 and U12 |
2 32-MB SIMMs |
MEM-NPE-128MB2 |
NPE-200 Memory Information
Table 1-5 provides information about memory specifications. Table 1-6 provides memory configurations for the NPE-200.
Table 1-5 NPE-200 Memory Specifications
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|
|
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Component Location on the NPE-200 Board
|
DRAM |
32 to 128 MB |
2 to 4 |
16- or 32-MB SIMMs (based on maximum DRAM required) |
Bank 0: U11 and U25 Bank 1: U42 and U52 |
SRAM |
4 MB |
8 |
8 chips, each being 512K x 8 bits wide |
U6, U10, U13, U14, U28, U29, U38, and U39 |
Boot ROM |
256 KB |
1 |
EPROM for the ROM monitor programs |
U92 |
Primary cache |
— |
— |
R5000 processor, internal cache |
U44 |
Secondary cache |
512 KB |
4 |
R5000 processor, unified, external cache |
U16, U9, U109, and U107 |
Table 1-6 NPE-200 DRAM SIMM Configurations—Configurable Memory Only
|
|
|
|
|
|
32 MB |
U11 and U25 |
2 16-MB SIMMs |
U42 and U52 |
— |
MEM-NPE-32MB2 |
64 MB |
U11 and U25 |
2 32-MB SIMMs |
U42 and U52 |
— |
MEM-NPE-64MB2 |
128 MB |
U11 and U25 |
2 32-MB SIMMs |
U42 and U52 |
2 32-MB SIMMs |
MEM-NPE-128MB2 |