Research at Cisco

Process, reliability, layout, circuit, architecture, simulation and performance of multi-gate transistors

Project ID:



Semiconductor multi-gate transistor with respect to architecture, design rule, process, simulation methodology, performance as well as reliability with performance degradation, aging and self-recovery


To improve semiconductor transistor off current, power and driving control, many technologies are using or developing multi-gate transistors such as the FINFET or TRIGATE transistor. Although most of the materials are the same as that used in planar transistors, due to its relatively new architecture, many new areas with this new structure need to be researched to fully understand its concerned items listed above.

Full Description:

Semiconductor transistors off currents have increased as technology scales. This is due to the scaling of threshold voltages to improve performance as the Vdd has scaled. To reduce the off current, semiconductor technologies have implemented or are developing mult-gate transistors for better off current control.

This technology change is a major structural change in the transistor. This can introduce many potential applications and challenges. Examples are:

  1. New reliability mechanisms or change (improve or degrade) existing mechanisms such as BTI, HCI, RTN or TDDB. The recovery mechanisms and behaviors may also change.
  2. The industry simulation method and infra-structure is not well established.
  3. The new design rule to fully leverage the advantage of multi-gate transistors in in its early stage.
  4. Proposals of research in collaboration with universities in these areas are needed.

Constraints and other information:

Cisco expects customary scholarly dissemination of results, and hopes that promising results would be made available to the community without limiting licenses, royalties, or other encumbrances.

Proposal submission:

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RFPs may be withdrawn as research proposals are funded, or interest in the specific topic is satisfied.
Submissions are batched and reviewed at the beginning of each calendar quarter in January, April, July, and October.

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