Research at Cisco

3D IC Integration and Enabling Technologies

Project ID:



3D IC Integration and Enabling Technologies


Over the past three decades, the semiconductor industry has been able to double the functionality of silicon devices every 18 months, as predicted by Moore's Law. However, economical and technical issues may slow down the scaling effort beyond the 22nm node. To continue reducing the cost per function, a possibility solution is to move to a 3 Dimensional (3D) stacking of ICs to bridge the gap between the capabilities of traditional 2D scaling and future system requirements.

Full Description:

The challenges being faced include, bandwidth improvement, power and form factor reduction, heterogeneous integration, and modular design requirements. By leveraging 3D IC integration, these challenges may be overcome.

The goal is to concurrently explore the technology and design issues associate with 3D technology applications for next generation high performance networking systems.

  • Design and characterization methodology for 3D IC assembly
    • Holistic design environment necessary to define and implement optimized 3D IC stacks
    • Spatial aware design methodology to co-optimize system and technology specifications
    • Low power, low latency chip to chip links (both parallel and serial)
  • Signal and power integrity and 3D interconnect modeling
    • Modeling of Through-Silicon-Vias and BEOL structures for high speed chip to chip links
    • Design and modeling of power delivering systems for 3D IC stacks
    • Power management
  • Cost model and assessment of impact to semiconductor supply chain
    • Manufacturing yield control and cost models
  • Thermal design and characterization methodology
    • Thermal analysis of 3D IC stacks
    • Innovative thermal management solutions for 3D IC integration
    • Thermo-mechanical modeling and testing of 3D IC stacks
    • Total stress management in 3D IC stacks
  • Testing and Manufacturing
    • Metrology techniques for 3DC IC characterization and manufacturing process control
    • At speed testing
    • TSV integrity testing
    • Known Good Die (KGD) solutions
  • Reliability
    • Failure mechanisms associated with 3D interconnect with TSV and acceleration models
    • Qualification methodologies for 3D IC stacks

Constraints and other information:

IPR will stay with the University. Cisco expects customary scholarly dissemination of results, and hopes that promising results would be made available to the community without limiting licenses, royalties, or other encumbrances.

Proposal submission:

Please use the link below to submit a proposal for research responding to this RFP. After a preliminary review, we may ask you to revise and resubmit your proposal.

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RFPs may be withdrawn as research proposals are funded, or interest in the specific topic is satisfied. Researchers should plan to submit their proposals as soon as possible. The deadline for Submissions is the Friday of the first week of each calendar quarter (the months of January, April, July, October). Funding decisions and communication will occur within 90 days from the quarterly submission deadline. The usage of funding is expected within 12 months of funding decision. Please plan your requests accordingly.

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