Power and Green Component and System Designs
According to Moore's Law, semiconductor manufacturing continues to scale down .5X in area every 2 years to provide 2X the functionality in a chip. While this trend is positive, there are a number of negative side effects, including increased transistor power density as operating voltage is not scaling as fast, and leakage current of transistors are increasing.
Common power reduction techniques with chip designs are:
In addition to the design mentioned above, we are looking for innovative ways to reduce both dynamic and static power. We are interested in, but not limited to, the following:
Constraints and other information:
IPR will stay with the University. Cisco expects customary scholarly dissemination of results, and hopes that promising results would be made available to the community without limiting licenses, royalties, or other encumbrances.
Please use the link below to submit a proposal for research responding to this RFP. After a preliminary review, we may ask you to revise and resubmit your proposal.
RFPs may be withdrawn as research proposals are funded, or interest in the specific topic is satisfied. Researchers should plan to submit their proposals as soon as possible. The deadline for Submissions is the Friday of the first week of each calendar quarter (the months of January, April, July, October). Funding decisions and communication will occur within 90 days from the quarterly submission deadline. The usage of funding is expected within 12 months of funding decision. Please plan your requests accordingly.
Questions? Contact: email@example.com