Semiconductor Reliability: Performance Degradation Over Lifetime, Aging and Self-Recovery
According to Moore's Law, semiconductor manufacturing continues to scale down .5X in area every two years to provide 2X the functionality in a chip. While this trend is positive, there are a number of negative side effects, including increased semiconductor parameter variability, increased aging effects, or degradation of device performance over device lifetime due to NBTI, PBTI & HC and performance degradation due to RTN.
To increase the operating margin, reliability and lifetime of next-generation products, we need a better understanding of the following reliability concerns:
- NBTI (Negative Bias Temperature Insatiability) & PBTI (Positive BTI): NBTI aging degrades the performance of P-channel devices and has become a significant reliability and yield concerns since 90 nm silicon technology. PBTI aging degrades the performance of the N-channel device and become a significant concern with the introduction of HKMG, High Gate Metal Gate, in 45 nm or 32 nm Silicon Technology. There is a partial recovery of performance when stress conditions are released. Area of interest but not limited to:
- SRAM Vmin: NBTI & PBTI together with increase in semiconductor parameter variability reduced the operating voltage window of SRAM memory. Vmin has been an industry concern since 90nm and has been getting worse with the coming of 22nm. Vmin is also depending on the amount of SRAM in a single chip
- CAD tool for design prediction and optimization: Operating frequency reduction of chips over time with the degradation of n-channel and P-channel devices. The existing CAD tools assume a single Vt degradation of all transistors and overestimate the effect of NBTI and PBTI without consideration of bias and recovery conditions. We need to reduce overdesign for smaller die sizes and use less power
- HTOL product performance measurement: For large, complex designs, the patterns applied in HTOL are generally logic BIST or scan, a memBIST, and IO tests, such as loop back for SERDES. However, these stress do not simulate applications and the ATE test is a delayed measurement. Solutions are required to simulate application reliability and detection of failure mechanism that may recover.
- Aging aware designs: Designs which account for BTI aging and recovery
- Materials and processing: Improvements to reduce the BTI effect and increase recovery
- HC (Hot Carrier degradation): Aggressive CMOS scaling have push the Hot Carrier challenges back to the front of device and circuit reliability discussions, the impacts of Channel Hot Carriers (CHC), Cold Carriers (CCC) and Non Conductive Hot-Carriers (NCHC). Area of interested but not limited to:
- Performance degradation
- Memory: SRAM & DRAM
- Design Mitigation
- Reliability measurement and prediction
- Materials and processing: Improvements to reduce the HCI effect
- RTN (Random Telegraph Noise): This is a noise mechanism due to the trapping/de-trapping of charge carriers at the MOS transistor Si-SiO2 interface. It manifests electrically as time dependent transistor Vt or current fluctuations which get worse with increasing temperature. RTN has become much more acute at the 45nm node with scaled transistor length and width. Area of interested but not limited to:
- SRAM Vmin:
- Test methodology to screen out RTN weak bits.
- Bit Cell design and design margin for RTN
- Logic delay fluctuation
- Other circuit issues due to RTN
- Aging effect
- Mitigation methods
- Failure rates
- Variations (including Random Dopant Fluctuation, Line Edge Roughness, etc): Silicon variations can cause marginality in silicon performance and reliability
- Any transistor or design techniques to model, simulate and account for variations to improve design performance and reliability.
- Other Simulation or Materials:
- Simulation, reliability stress, modeling, prediction or device physics of any reliability mechanism
- Transistor and routing improvements such as new materials, dielectrics or conductors
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