Research at Cisco

Logic In-Field Repair Research

Project ID:


RFP-2010-063

Title:


Logic In-Field Repair Research

Summary:


Semiconductor manufacturing continues to provide smaller feature sizes resulting in lower power, higher density, and lower cost per function. While this trend is positive, there are a number of negative side effects, including increased semiconductor parameter variability, increased sensitivity to soft errors, and lower device yields. The lifetime of next-generation devices is also decreasing due to lower reliability margins and shorter product lifetimes. To increase the reliability, availability, and lifetime of next-generation products, new methods for in-field repair or "design for repair" or "self-healing" are needed.

Techniques that exploit in-field repair for memories and interconnect have been used for years in general-purpose systems. These techniques include reconfigurable duplication, hot swapping, backup sparing, graceful degradation, and resource reconfiguration. In each of these cases, an in-field graceful repair action takes place after a mechanism for detecting faults.

While these techniques have been successful in memory and interconnect, in-field repair has not generally been applied to logic structures (i.e., sequential such as latch, FF, etc. and combinational logic such as buffer). The general method such as fault detection, fault isolation and then fault repair are highly challenging. Here we call for proposal in this area of research. A proposal should high light the approaches, planned the research within this objective.

Full Description:


Moore Law has been shrinking the technology feature size, and increasing the number of transistors on a chip by about 2x every 18 months. This rapid and continuous technology scaling has required the development of new lithography techniques and pattern transfer onto the materials on the silicon wafers. New materials are being used for gates and gate dielectrics. Improved electron and hole mobility has been achieved through improve stress engineering. Metal delays have been reduced by using materials with lower dielectric constants. All these changes not only increase the complexity of the semiconductor processing, but they also help to pack more transistors on the our chips.

Although the trend is positive there are a number of negative side effects. The power per transistor is decreasing but the increasing clock frequency and number or transistor have led to higher overall power. The higher power leads to higher junction temperatures which reduces the overall reliability. The smaller geometry also creates larger variability in the transistors which can cause variability in Vddmin, NBTI and HCI characteristics. This scaling of voltages has not kept up with the scaling of the geometries. This give us higher electric fields for better performance, but this scaling has also reduced the reliability margin and wear out lifetimes of our devices. The use of new materials can also introduce new failure mechanisms in the silicon die.

To increase the reliability, availability, and lifetime of next-generation products, new methods for in-field repair or "design for repair" or "self-healing" are needed. Techniques that exploit in-field repair for memories and interconnect have been used for years in general-purpose systems. These techniques include reconfigurable duplication, hot swapping, backup sparing, graceful degradation, and resource reconfiguration. In each of these cases, an in-field graceful repair action takes place after a mechanism for detecting faults.

While these techniques have been successful in memory and interconnect, in-field repair has not generally been applied to logic structures (i.e., sequential such as latch, FF, etc. and combinational logic such as buffer). Methodologies for logic fault detection, fault isolation and then fault repair are highly challenging. Repair should be accomplished quickly and with minimal overhead for repair time, die area and power. A proposal should high light the approaches, and planned research within this objective.

Constraints and other information:


IPR will stay with the University. Cisco expects customary scholarly dissemination of results, and hopes that promising results would be made available to the community without limiting licenses, royalties, or other encumbrances.

Proposal submission:


Please use the link below to submit a proposal for research responding to this RFP. After a preliminary review, we may ask you to revise and resubmit your proposal.

Submit a proposal for this RFP this link will generate a new window

Note: RFPs may be withdrawn as research proposals are funded, or interest in the specific topic is satisfied. Researchers should plan to submit their proposals as soon as possible. The deadline for Submissions is the Friday of the first week of each calendar quarter (the months of January, April, July, October). Funding decisions and communication will occur within 90 days from the quarterly submission deadline. The usage of funding is expected within 12 months of funding decision. Please plan your requests accordingly.

Questions? Contact: research@cisco.com