RFP-Based Research Proposal

Project ID:

RFP-2008-045

Title:

Robust Logic and Flip-Flop Design

Summary:

Silicon technology scaling at 65nm and below is exposing logic designs to new potential failure mechanisms that have not been sufficiently investigated. Specific areas of interest include:

• creation of flip-flops robust to Single Event Upset (SEU),
• guidelines for prioritized use of robust components, and
• methods for better understanding temporal masking effects at small geometries.

The question is: what steps need to be taken to optimize SEU-resilient designs as geometries continue to shrink?

Full Description:

Cisco encourages research to develop and quantify different SEU resilient or hardened flip-flops that will benefit advanced ASIC based products. We are aware of at least three areas where research could lead to significant impact on small-geometry ASIC design.

1. Single Event Upset (SEU) resilient flip-flop design and characterization. Such logic blocks would be designed and verified to provide significantly lower exposure to SEU's. The key is to minimize the negative trade off of die area, chip power, and performance impact of such flip-flops, to the point where the flip-flops can be deployed broadly or universally. The goal is to have at least a 10X improvement in the SEU failure rate compared to conventional flip-flops with minimum negative impact.
2. Design flow methodologies to optimize SEU resilient flip-flop (F/F) insertion. SEU resilient flip-flops may have negative impact on flip-flop area, power, and/or performance. A design methodology that optimizes the logic and layout insertion of SEU resilient F/F's could reduce this SEU resilient design overhead. To minimize the die area, power and performance impact from replacement SEU resilient flip-flops, it is vital to replace the most SEU-critical flip-flops - which are often based on either critical function, state or data path. Successful research might provide direction and methodology for the placement/replacement of flip-flops with some simple calculation for the F/F soft error rate to estimate the gross improvement.
3. Temporal masking study for 45nm technology and beyond. Continued silicon technology scaling will bring new design challenges with large gate delay variability due to small transistor geometry, low and variable Vt, thin gate oxide, local doping fluctuation, etc. Proposals might explore how to simulate temporal masking effects that arise from this larger gate delay variability in a large integration ASIC chip. Scale-induced increases in wafer-to-wafer, die-to-die and within-die variability complicates temporal masking computations for SEU simulation in a real design, since the above issues combine, and increase the complexity of timing analysis. If we consider only the most conservative case (fast corner), then we gain very little from temporal masking because all paths have huge slack. We seek better understanding of which assumptions are reasonable, and how to justify these assumptions. Expected benefits might include more accurate Failure In Time (FIT) computation for ASIC design, which could minimize other unnecessary hardware mitigation efforts.

Constraints and other information:

IPR will stay with the University. Cisco expects customary scholarly dissemination of results, and hopes that promising results would be made available to the community without limiting licenses, royalties, or other encumbrances.

Proposal submission:

Please use the link below to submit a proposal for research responding to this RFP. After a preliminary review, we may ask you to revise and resubmit your proposal.

Create/submit a proposal for this RFP

RFPs may be withdrawn as research proposals are funded, or interest in the specific topic is satisfied. Researchers should plan to submit their proposals as soon as possible. Submissions-to-date are reviewed at the beginning of each quarter (the first business day of: January, April, July, October).

Questions? Contact: research@cisco.com