Project ID:
RFP-2007-014
Title:
Multi-core Modeling and Memory Optimization with Disparate Operating Systems
Summary:
Multi-core System on Chip (SOC) packaging in increasingly popular. However, methods for optimizing utilization of memory subsystems are not well-understood. For example, 4, 8, and 16 core systems often contain per-core L1-caches, while sharing L2 caches and external memory systems. When cores run disparate operating systems, or perhaps core-specific applications, we need better methods for modeling and optimizing inter-core memory operations. The question is, how can we optimize utilization of memory in multi-core, multi-OS, embedded environments, such as networking systems/applications?
Full Description:
Multi-core CPU's are often packaged as Systems on Chip (SOC) with rich, flexible memory hierarchies. This same flexibility can make modeling and performance prediction of inter-core memory operations problematic. We believe the design community would be well-served by a deeper understanding of the tradeoffs and interactions among data flow, cache-partitioning, and memory controller design.
For example, most SOC's come with built in L1/L2 caches and external DDR memory controllers. The L1 Instruction and Data caches are dedicated to each core; their sizing is critical to system performance. On the other hand, the L2 cache is much larger and shared by all the cores in some manner - either shared uniformly, or partitioned per core / group of cores. The sharing mechanism is often via partitioning "by way" for an n-way L2 cache. Additionally, the optimal size of the cache-line fill is usually application dependent.
External memory is typically high-speed DDR (DDR2/3) DRAM. Memory controller design is a key issue, employing techniques like hiding external memory latency by keeping multiple memory pages open as long as possible, or grouping sequential writes in the same column.
Each of the above elements influence overall system performance, and impact the effectiveness of inter-core communication (for payload data, control information, or statistics). Modeling and optimization are further complicated when cores run different types of software. For instance, two or more cores might be run SMP Linux while one or more other cores run simple 'C' routines for special purpose data manipulation. This environment also makes optimized locking of shared data structures or other resources more difficult.
We invite proposals that explore how to model and predict the performance of these cores in order to optimize the size of the caches, partitioning of the L2 shared cache, external memory usage, memory controller scheduling algorithms, locking of shared resources, and core-to-core interprocess communications under a variety application execution scenarios.
Constraints and other information:
IPR will stay with the University. Cisco expects customary scholarly dissemination of results, and hopes that promising results would be made available to the community without limiting licenses, royalties, or other encumbrances.
Proposal submission:
Cisco is not currently accepting proposals for this RFP.
Questions? Contact: research@cisco.com
