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Table Of Contents
Supported Standards, MIBs, and RFCs
Per VC Error Display
The show controllers atm command was modified:
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To enable the output of CRC error counts on a per-VC basis
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Supported Platforms
This feature is supported on the Cisco 6400 node route processor (NRP).
Supported Standards, MIBs, and RFCs
None
Configuration Tasks
None
Command Reference
show controllers atm
To display information on the physical ATM interface of the Cisco 6400 NRP, use the show controllers atm 0/0/0 privileged EXEC command.
show controllers atm 0/0/0 [detailed | scheduler | vc vpi/vci]
Syntax Description
Defaults
The default output shows only SAR controller information.
Command Modes
Privileged EXEC
Command History
Examples
In the following example, the output consists only of the SAR controller information:
NRP# show controllers atm 0/0/0Interface ATM0/0/0Hardware is ATM-SARPCI registers:bus_no=0, device_no=4CFID=0xA102104C, CFCS=0x02000006, CFRV=0x02030002, CFLT=0x0000FF00CFBA=0x4A000000, CFIT=0x02010100*** TI1575 SAR at address 0x3A000000 ***Receive/Transmit Statisticsrx_isrs: 0 rx_isr_pkts: 1 rx_isr_bufs: 0rx_cells_ovf: 0 tx_cells_ovf: 0 hec_errors_ovf: 0rx_unkn_prot: 314 rx_aal5_disc: 0 rx_pkt_ovf: 0unkn_prot_ovf:0 aal5_disc_ovf: 0 tx_count: 0rx_crc_error: 0 rx_no_buf: 0 rx_timeout: 0rx_abort: 0 rx_cong_cells: 0 rx_freeze: 0rx_no_valbuf: 0 rx_bad_vc: 0 fallback act: 0tx_abort: 0 tx_no_desc: 0 tx_align: 0tx_freeze: 0 disabled: 0 enabled: 0tx_clones: 0 tx_xmt_paks: 3 teardown_vc: 0tx_pend_count_negative: 0tx_forced: 0 (0)tx_max_queued: 6144 seg_ring_size: 32tx output drops: 0pkt_too_big: 0 tx_pak_failed: 0idb_down: 0 invalid_pkt_type: 0invalid_vcd: 0 vc_ring_full: 0over_max_queued: 0 slot_owned_by_chip: 0vc_not_in_use: 0invalid_addr_count: 0PCI Statisticsdetect_parity 0 system_error 0 master_abort 0rx_target_abort 0 sig_target_abort 0 data_parity 0Internal registersconfig: 0x6037 status: 0x2000040 imask: 0xC381ratcount: 0x800 globrat: 0x79 rxunkn: 0x10000010txcompsize: 0x7FF rxcompsize: 0x1FF txsegsize: 0x1Faal5discard:0x0 hecerrors: 0x0 unknprot: 0x14Crxcells: 0x1 txcells: 0x1B schedsize: 0x1txqueue: 0x80002009(spinerr:0) txpause: 0x0 chancount: 0x5txcompring: 0x311A00C rxcompring: 0x3114020Structures common to all VCsreceive free buffer ringaddress: 0x3110820 buf size: 10 ring size: 63 sar_indx: 1 drv_indx: 1receive completion ringaddr: 0x3114000 indx: 1transmit completion ringaddr: 0x311A000 indx: 3In the following example, the output consists of all available information:
NRP# show controllers atm 0/0/0 detailedInterface ATM0/0/0Hardware is ATM-SARPCI registers:bus_no=0, device_no=4CFID=0xA102104C, CFCS=0x02000006, CFRV=0x02030002, CFLT=0x0000FF00CFBA=0x4A000000, CFIT=0x02010100*** TI1575 SAR at address 0x3A000000 ***Receive/Transmit Statisticsrx_isrs: 0 rx_isr_pkts: 1 rx_isr_bufs: 0rx_cells_ovf: 0 tx_cells_ovf: 0 hec_errors_ovf: 0rx_unkn_prot: 514 rx_aal5_disc: 0 rx_pkt_ovf: 0unkn_prot_ovf:0 aal5_disc_ovf: 0 tx_count: 0rx_crc_error: 0 rx_no_buf: 0 rx_timeout: 0rx_abort: 0 rx_cong_cells: 0 rx_freeze: 0rx_no_valbuf: 0 rx_bad_vc: 0 fallback act: 0tx_abort: 0 tx_no_desc: 0 tx_align: 0tx_freeze: 0 disabled: 0 enabled: 0tx_clones: 0 tx_xmt_paks: 3 teardown_vc: 0tx_pend_count_negative: 0tx_forced: 0 (0)tx_max_queued: 6144 seg_ring_size: 32tx output drops: 0pkt_too_big: 0 tx_pak_failed: 0idb_down: 0 invalid_pkt_type: 0invalid_vcd: 0 vc_ring_full: 0over_max_queued: 0 slot_owned_by_chip: 0vc_not_in_use: 0invalid_addr_count: 0PCI Statisticsdetect_parity 0 system_error 0 master_abort 0rx_target_abort 0 sig_target_abort 0 data_parity 0Internal registersconfig: 0x6037 status: 0x2000040 imask: 0xC381ratcount: 0x800 globrat: 0x79 rxunkn: 0x10000010txcompsize: 0x7FF rxcompsize: 0x1FF txsegsize: 0x1Faal5discard:0x0 hecerrors: 0x0 unknprot: 0x214rxcells: 0x1 txcells: 0x1B schedsize: 0x1txqueue: 0x80002009(spinerr:0) txpause: 0x0 chancount: 0x5txcompring: 0x311A00C rxcompring: 0x3114020Structures common to all VCsreceive free buffer ringaddress: 0x3110820 buf size: 10 ring size: 63 sar_indx: 1 drv_indx: 1receive completion ringaddr: 0x3114000 indx: 1transmit completion ringaddr: 0x311A000 indx: 3*** VC information and associated 1575 structures ***seg ring: 5 ringaddr: 0x311C400 ringindx:0 pendindx:0tx dma: 5 ctrlring: 0xC47100 pktcnt: 0rword10: 0x0 rword11: 0x0rword20: 0x0 rword21: 0x0 rword22: 0x0 rword23: 0x0pxmt 0 queued: 0VCs mapped to this ringvcd: 1 cellhdr: 0x1E00640 encap: 0 crcerror: 0rx dma: 5 config: 0x24000000 ctrlrxring: 0x80000200 timecnt: 0xC8000lookup: 2 channel: 5 vpivci: 0x1E0064seg ring: 6 ringaddr: 0x311C480 ringindx:0 pendindx:0tx dma: 6 ctrlring: 0xC47120 pktcnt: 0rword10: 0x0 rword11: 0x0rword20: 0x0 rword21: 0x0 rword22: 0x0 rword23: 0x0pxmt 0 queued: 0VCs mapped to this ringvcd: 2 cellhdr: 0x2800C80 encap: 0 crcerror: 0rx dma: 6 config: 0x24000000 ctrlrxring: 0x80000400 timecnt: 0xC8000lookup: 3 channel: 6 vpivci: 0x2800C8seg ring: 7 ringaddr: 0x311C500 ringindx:0 pendindx:0tx dma: 7 ctrlring: 0xC47140 pktcnt: 0rword10: 0x0 rword11: 0x0rword20: 0x0 rword21: 0x0 rword22: 0x0 rword23: 0x0pxmt 0 queued: 0VCs mapped to this ringvcd: 3 cellhdr: 0xA0 encap: 0 crcerror: 0rx dma: 7 config: 0x24000000 ctrlrxring: 0x80000600 timecnt: 0xC8000lookup: 0 channel: 7 vpivci: 0xAseg ring: 8 ringaddr: 0x311C580 ringindx:0 pendindx:0tx dma: 8 ctrlring: 0xC47160 pktcnt: 0rword10: 0x0 rword11: 0x0rword20: 0x0 rword21: 0x0 rword22: 0x0 rword23: 0x0pxmt 0 queued: 0VCs mapped to this ringvcd: 4 cellhdr: 0x500 encap: 0 crcerror: 0rx dma: 8 config: 0x24000000 ctrlrxring: 0x80000800 timecnt: 0xC8000lookup: 1 channel: 8 vpivci: 0x50seg ring: 9 ringaddr: 0x311C600 ringindx:3 pendindx:3tx dma: 9 ctrlring: 0xC47183 pktcnt: 0rword10: 0x663C0000 rword11: 0x33CE274rword20: 0x0 rword21: 0x33CDFC4 rword22: 0x0 rword23: 0x0pxmt 0 queued: 0VCs mapped to this ringvcd: 5 cellhdr: 0x3200640 encap: 0 crcerror: 0rx dma: 9 config: 0x24000000 ctrlrxring: 0x80000A00 timecnt: 0xC8000lookup: 4 channel: 9 vpivci: 0x320064*** TI1585/1585 Scheduler at address 0x3A040000 ***Configuration/Statisticsline bw: 149760 min vc bw: 64 total slots: 2free slots: 21585 internal registersconfig: 0x227 status: 0x1E imask: 0x0clkfreq: 0x18FCA1 revnum: 0x0 acrlow: 0x80000000acrok: 0x800000001585 connection config/statusscheduler id 5type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 6type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 7type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 8type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 9type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100In the following example, the output consists of only the SAR scheduler information:
NRP# show controllers atm 0/0/0 schedulerInterface ATM0/0/0Hardware is ATM-SARPCI registers:bus_no=0, device_no=4CFID=0xA102104C, CFCS=0x02000006, CFRV=0x02030002, CFLT=0x0000FF00CFBA=0x4A000000, CFIT=0x02010100*** TI1585/1585 Scheduler at address 0x3A040000 ***Configuration/Statisticsline bw: 149760 min vc bw: 64 total slots: 2free slots: 21585 internal registersconfig: 0x227 status: 0x1E imask: 0x0clkfreq: 0x18FCA1 revnum: 0x0 acrlow: 0x80000000acrok: 0x800000001585 connection config/statusscheduler id 5type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 6type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 7type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 8type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100scheduler id 9type: VBR pcr: 353207 scr: 353207 mbs: 91rtv: 0x100In the following example, the VC output consists only of information specific to VC 50/100:
NRP# show controllers atm 0/0/0 vc 50/100Interface ATM0/0/0Hardware is ATM-SARPCI registers:bus_no=0, device_no=4CFID=0xA102104C, CFCS=0x02000006, CFRV=0x02030002, CFLT=0x0000FF00CFBA=0x4A000000, CFIT=0x02010100*** VC information and associated 1575 structures ***seg ring: 9 ringaddr: 0x311C600 ringindx:3 pendindx:3tx dma: 9 ctrlring: 0xC47183 pktcnt: 0rword10: 0x663C0000 rword11: 0x33CE274rword20: 0x0 rword21: 0x33CDFC4 rword22: 0x0 rword23: 0x0pxmt 0 queued: 0VCs mapped to this ringvcd: 5 cellhdr: 0x3200640 encap: 0 crcerror: 0rx dma: 9 config: 0x24000000 ctrlrxring: 0x80000A00 timecnt: 0xC8000lookup: 4 channel: 9 vpivci: 0x320064In the following example, the output displays CRC error counters for each configured VC:
NRP# show controllers atm 0/0/0 detailed | include crcrx_crc_error: 0 rx_no_buf: 0 rx_timeout: 0vcd: 1 cellhdr: 0x1E00640 encap: 0 crcerror: 0vcd: 2 cellhdr: 0x2800C80 encap: 0 crcerror: 0vcd: 3 cellhdr: 0xA0 encap: 0 crcerror: 0vcd: 4 cellhdr: 0x500 encap: 0 crcerror: 0vcd: 5 cellhdr: 0x3200640 encap: 0 crcerror: 0Related Commands
Glossary
CRC—cyclic redundancy check. Error-checking technique in which the frame recipient calculates a remainder by dividing frame contents by a prime binary divisor and compares the calculated remainder to a value stored in the frame by the sending node.
SAR—segmentation and reassembly. One of the two sublayers of the AAL CPCS, responsible for dividing (at the source) and reaassembling (at the destination) the PDUs passed from the CS. The SAR sublayer takes the PDUs processed by the CS and, after dividing them into 48-byte pieces of payload data, passes them to the ATM layer for further processing.
VC—virtual channel. Logical circuit created to ensure reliable communication between two network devices. A VC is defined by a VPI/VCI pair, and can be either permanent (PVC) or switched (SVC).