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Broadband Access Aggregation and DSL Configuration Guide, Cisco IOS Release 12.4T
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ATM Mode for Two-Wire or Four-Wire SHDSL
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Contents
ATM Mode for Two-Wire or Four-Wire SHDSLLast Updated: December 5, 2011
This document describes the ATM Mode for Two-Wire or Four-Wire SHDSL feature on the Cisco 1700 series, Cisco 1800 series, Cisco 26xxXM, Cisco 2691, Cisco 2800, Cisco 3700 series, and Cisco 3800 series routers. The ATM Mode for Two-Wire or Four-Wire SHDSL feature adds 4-wire support in fixed line-rate mode only on a WIC-1SHDSL-V2 or WIC-1SHDSL-V3 interface card. 2-wire mode supports 2-wire line-rate and auto line-rate. This feature builds on the existing features of the Multirate Symmetrical High-Speed Digital Subscriber Line (G.SHDSL) feature supported on the 1-port G.SHDSL WAN interface card (WIC-1SHDSL). The 4-wire feature of G.991.2 doubles the bandwidth in ATM mode and increases usable distance over two pairs of wires. The WIC-1SHDSL-V2 and WIC-1SHDSL-V3 support ATM on 2-wire and 4-wire line mode. Embedded Operation Channel (EOC) messages support for customer premises equipment (CPE) is provided for 2-wire and 4-wire modes.
Finding Feature InformationYour software release may not support all the features documented in this module. For the latest feature information and caveats, see the release notes for your platform and software release. To find information about the features documented in this module, and to see a list of the releases in which each feature is supported, see the Feature Information Table at the end of this document. Use Cisco Feature Navigator to find information about platform support and Cisco software image support. To access Cisco Feature Navigator, go to www.cisco.com/go/cfn. An account on Cisco.com is not required. Prerequisites for ATM Mode for Two-Wire or Four-Wire SHDSL
Restrictions for ATM Mode for Two-Wire or Four-Wire SHDSL
Information About ATM Mode for Two-Wire or Four-Wire SHDSL
SHDSL FeaturesSupported SHDSL features are as follows:
ATM FeaturesThe supported ATM features in this release are:
Interface and Controller Numbering on the Cisco 1721 RouterIf a WIC-1SHDSL-V2 or WIC-1SHDSL-V3 is installed in a Cisco 1721 router, the interfaces and controllers are assigned numbers based on a numbering scheme that is different from the slot numbering scheme on other Cisco routers. This is because the Cisco 1721 router assigns only a slot number without also assigning a port number. Other Cisco routers typically use a slot and port number combination. If a WIC-1SHDSL-V2 or WIC-1SHDSL-V3 (the DSL controller) is installed in slot 0, the ATM interfaces (ADSL/SHDSL) will be numbered relative to the DSL controller in slot 0. See the table below for examples of the slot numbering scheme on the Cisco 1721 router. With an ATM card in slot 0, the WIC-1SHDSL-V2 or WIC-1SHDSL-V3 in slot 1 will be numbered relative to the number of ports in slot 0. If both slots are occupied by DSL controllers, the logical interfaces configured on each controller will have the same number as the slot occupied by the DSL controller. All logical interfaces on the WIC-1SHDSL-V2 will have the same number as the DSL controller.
Interface Numbering on Cisco 2800 and Cisco 3800 Series RoutersThis section describes the interface numbering scheme for Cisco 2800 and Cisco 3800 series routers. If an interface card is installed in a Cisco 2800 series or Cisco 3800 series router, the interfaces must use a triple-number scheme to identify them. This triple-number assignment is different from the standard interface numbering scheme on other Cisco routers. The table below shows the interface numbering for the onboard Fast Ethernet ports and the interface slots on Cisco 2800 and Cisco 3800 series routers.
How to Configure ATM Mode for Two-Wire or Four-Wire SHDSL
Configuring G.SHDSL ServiceThis section details how to configure the ATM Mode for Two-Wire or Four-Wire SHDSL feature for G.SHDSL service. To configure G.SHDSL service in ATM mode on a Cisco router containing a G.SHDSL WIC, complete the steps in the Summary Steps or the Detailed Steps, beginning in global configuration mode. Before You Begin
SUMMARY STEPS
The following list of prerequisites should be followed for this configuration:
DETAILED STEPS Verifying the ATM Configuration
SUMMARY STEPS
DETAILED STEPS
ExamplesThe following example shows how the show interface atmcommand is used and that the ATM slot/port and line protocol are up: Router# show interfaces atm 0/0 ATM0/0 is up, line protocol is up Hardware is DSLSAR MTU 4470 bytes, sub MTU 4470, BW 4608 Kbit, DLY 110 usec, reliability 0/255, txload 1/255, rxload 1/255 Encapsulation ATM, loopback not set Encapsulation(s): AAL5 , PVC mode 23 maximum active VCs, 256 VCs per VP, 1 current VCCs VC Auto Creation Disabled. VC idle disconnect time: 300 seconds Last input never, output never, output hang never Last clearing of "show interface" counters never Input queue: 0/75/0/0 (size/max/drops/flushes); Total output drops: 0 Queueing strategy: Per VC Queueing 30 second input rate 0 bits/sec, 0 packets/sec 30 second output rate 0 bits/sec, 0 packets/sec 0 packets input, 0 bytes, 0 no buffer Received 0 broadcasts, 0 runts, 0 giants, 0 throttles 0 input errors, 0 CRC, 0 frame, 0 overrun, 0 ignored, 0 abort 0 packets output, 0 bytes, 0 underruns 0 output errors, 0 collisions, 1 interface resets 0 output buffer failures, 0 output buffers swapped out 3725# show atm vc VCD / Peak Avg/Min Burst Interface Name VPI VCI Type Encaps SC Kbps Kbps Cells Sts 0/0.1 1 2 100 PVC MUX VBR 2000 2000 0 UP 0/1.1 1 2 100 PVC SNAP CBR 4608 UP 0/2.1 1 2 100 PVC SNAP VBR 4608 4200 0 UP 1/0.1 1 2 100 PVC SNAP VBR 4608 4608 0 UP 3725# Router# show atm vc VCD / Peak Avg/Min Burst Interface Name VPI VCI Type Encaps SC Kbps Kbps Cells Sts 1/0.3 2 9 36 PVC MUX UBR 800 UP 1/0.2 1 9 37 PVC SNAP UBR 800 UP 3725# show controllers atm 0 / 0 Interface: ATM0/0, Hardware: DSLSAR, State: up IDB: 645F4B98 Instance: 645F646C reg_dslsar:3C200000 wic_regs: 3C200080 PHY Inst:0 Ser0Inst: 645DFC8C Ser1Inst: 645EA608 us_bwidth:4608 Slot: 0 Unit: 0 Subunit: 0 pkt Size: 4528 VCperVP: 256 max_vp: 256 max_vc: 65536 total vc: 1 rct_size:65536 vpivcibit:16 connTblVCI:8 vpi_bits: 8 vpvc_sel:3 enabled: 0 throttled: 0 cell drops: 0 Last Peridic Timer 00:44:26.872(2666872) Parallel reads to TCQ:0 tx count reset = 0, periodic safe start = 0 Attempts to overwrite SCC txring: 0 Host Controller lockup recovery Info: recovery count1= 0, recovery count2= 0 Saved Host Controller Info to check any lockup: scc = 0, output_qcount = 0, head:0, buf addr = 0x00000000, serial outputs = 0 scc = 1, output_qcount = 0, head:54, buf addr = 0x00000000, serial outputs = 212 Serial idb(AAL5) output_qcount:0 max:40 Serial idb(RAW) output_qcount:0, max:40 Sar ctrl queue: max depth = 0, current queue depth = 0, drops = 0, urun cnt = 0, total cnt = 106 Serial idb tx count: AAL5: 0, RAW: 212, Drop count:AAL5: 0, RAW: 0 Host Controller Clock rate Info: SCC Clockrates: SCC0 = 1000000 (ATM0/0) SCC1 = 8000000 (ATM0/0) SCC2 = 1000000 (ATM0/1) SCC3 = 1000000 (ATM0/2) SCC4 = 5300000 (ATM0/1) SCC5 = 8000000 (ATM0/2) SCC6 = 0 SCC7 = 0 WIC Register Value Notes --------------- ---------- ---------- FPGA Dev ID (LB) 0x53 'S' FPGA Dev ID (UB) 0x4E 'N' FPGA Revision 0xA7 WIC Config Reg 0x35 WIC / VIC select = WIC; CTRLE addr bit 8 = 0; NTR Enable = 0; OK LED on; LOOPBACK LED off; CD LED on; WIC Config Reg2 0x07 Gen bus error on bad G.SHDSL ATM/T1/E1 access Int 0 Enable Reg 0x01 G.SHDSL ATM/T1/E1 normal interrupt enabled G.SHDSL ATM/T1/E1 error interrupt disabled DSLSAR Register Value Notes --------------- ---------- ---------- sdram_refresh: 0x410FFFF Expected value: 0x428xxxx intr_event_reg: 0xC0 TMR. intr_enable_reg: 0x13C FIFOF.FBQE.RQAF.RPQAF.TSQAF. config: 0x660D0A20 UTOPIA.RXEN.RegulateXmit.RMCell.TXEN. Rx Buffer size: 8192. RCT: Large, VPI Bits: 8. status: 0x0 clkPerCell: 814121 (line rate: 4608 Kbps) Pre-timer Count: 461 rcid_tableBase: 0x0 rct_base: 0x10000 tstBase1: 0x13C28 TST boot jump. rawCellBase: 0x14300 (0/128) slots used. rpq_base: 0x16000 tsqb(Tx Stat Q): 0x17000 fbq_base: 0x17880 (fbq_count: 128) txChanQueue: 0x18000 rxBuffers: 0x30000 txBuffers: 0x130000 Lookup Error cnt: 0x0 Invalid Cell cnt: 0x0 SCCA Rx Errors: 0x0 SCCB Rx Errors: 0x0 Drop Pkt Count: 0x0 Total Tx Count: 0x0 Total Rx Count: 0x0 Timer: 0x73A141 DSLSAR Interrupts:0x0 Last Addr:0x12E14 Router# show controllers atm 1 / 0 Interface ATM1/0 is up Hardware is DSLSAR (with Globespan G.SHDSL Module) IDB: 62586758 Instance:6258E054 reg_dslsar:3C810000 wic_regs:3C810080 PHY Inst:62588490 Ser0Inst:62573074 Ser1Inst: 6257CBD8 us_bwidth:800 Slot: 1 Unit: 1 Subunit: 0 pkt Size:4496 VCperVP:256 max_vp: 256 max_vc: 65536 total vc:2 rct_size:65536 vpivcibit:16 connTblVCI:8 vpi_bits:8 vpvc_sel:3 enabled: 0 throttled:0 WIC Register Value Notes --------------- ---------- ---------- WIC Config Reg 0x45 WIC / VIC select = WIC; CTRLE addr bit 8 = 1; OK LED on; LOOPBACK LED off; CD LED on; WIC Config Reg2 0x07 Gen bus error on bad ADSL access Int 0 Enable Reg 0x03 ADSL normal interrupt enabled ADSL error interrupt enabled What to Do NextVerify the configuration using the detailed steps in the Verifying DSL Configuration. Verifying DSL Configuration
SUMMARY STEPS
DETAILED STEPS
ExamplesThe following example shows how to verify 4-wire ATM mode in line zero (CPE):
Router# show controller dsl 0/0
DSL 0/0 controller UP
Globespan xDSL controller chipset
Line Mode: Four Wire
DSL mode: Trained with SHDSL Annex B
Frame mode: Utopia
Configured Line rate: 4608Kbps
Line Re-activated 9 times after system bootup
LOSW Defect alarm: ACTIVE
CRC per second alarm: ACTIVE
Line termination: CPE
FPGA Revision: 0xB3
Line 0 statistics
Current 15 min counters
CRC : 0 LOSW Defect : 0 ES : 0 SES : 0 UAS : 25
Previous 15 min counters
CRC : 0 LOSW Defect : 0 ES : 0 SES : 0 UAS : 0
Current 24 hr counters
CRC : 0 LOSW Defect : 4 ES : 0 SES : 0 UAS : 25
Previous 24 hr counters
CRC : 5 LOSW Defect : 4 ES : 1 SES : 0 UAS : 19
Line 1 statistics
Current 15 min counters
CRC : 0 LOSW Defect : 0 ES : 0 SES : 0 UAS : 25
Previous 15 min counters
CRC : 0 LOSW Defect : 0 ES : 0 SES : 0 UAS : 0
Current 24 hr counters
CRC : 0 LOSW Defect : 0 ES : 0 SES : 0 UAS : 25
Previous 24 hr counters
CRC : 6 LOSW Defect : 4 ES : 1 SES : 0 UAS : 19
Line-0 status
Chipset Version: 0
Firmware Version: R3.0.1
Modem Status: Data, Status 1
Last Fail Mode: No Failure status:0x0
Line rate: 2312 Kbps
Framer Sync Status: In Sync
Rcv Clock Status: In the Range
Loop Attenuation: 0.0 dB
Transmit Power: 9.5 dB
Receiver Gain: 19.5420 dB
SNR Sampling: 37.6080 dB
Line-1 status
Chipset Version: 0
Firmware Version: R3.0.1
Modem Status: Data, Status 1
Last Fail Mode: No Failure status:0x0
Line rate: 2312 Kbps
Framer Sync Status: In Sync
Rcv Clock Status: In the Range
Loop Attenuation: 0.0 dB
Transmit Power: 9.5 dB
Receiver Gain: 19.5420 dB
SNR Sampling: 37.6080 dB
Dying Gasp: Present
Sample Output--Building Configuration
Router> show running-config
Current configuration : 3183 bytes
!
version 12.3
service timestamps debug uptime
service timestamps log uptime
no service password-encryption
!
hostname 3725
!
boot-start-marker
boot system flash c3725-is-mz.0424
boot system tftp shriv/c3725-is-mz.new 223.255.254.254
boot-end-marker
!
!
memory-size iomem 25
no network-clock-participate slot 1
no network-clock-participate slot 2
no network-clock-participate wic 0
no network-clock-participate wic 1
no network-clock-participate wic 2
no network-clock-participate aim 0
no network-clock-participate aim 1
no aaa new-model
ip subnet-zero
ip cef
!
!
!
!
!
!
!
controller DSL 0/0
mode atm
line-term co
line-mode 4-wire
dsl-mode shdsl symmetric annex B
line-rate 4608
!
controller DSL 0/1
mode atm
line-term co
line-mode 4-wire
dsl-mode shdsl symmetric annex B
line-rate 4608
controller DSL 0/2
mode atm
line-term co
line-mode 4-wire
dsl-mode shdsl symmetric annex B
line-rate 4608
!
controller DSL 1/0
mode atm
line-term co
line-mode 4-wire
dsl-mode shdsl symmetric annex B
line-rate 4608
!
!
!
interface ATM0/0
no ip address
load-interval 30
no atm ilmi-keepalive
clock rate aal5 8000000
!
interface ATM0/0.1 point-to-point
ip address 5.0.0.1 255.0.0.0
pvc 2/100
vbr-rt 2000 2000
oam-pvc 0
encapsulation aal5mux ip
!
!
interface FastEthernet0/0
ip address 1.3.208.25 255.255.0.0
duplex auto
speed auto
no cdp enable
!
interface ATM0/1
no ip address
load-interval 30
no atm ilmi-keepalive
clock rate aal5 5300000
!
interface ATM0/1.1 point-to-point
ip address 6.0.0.1 255.0.0.0
pvc 2/100
cbr 4608
!
!
interface FastEthernet0/1
mac-address 0000.0000.0011
ip address 70.0.0.2 255.0.0.0 secondary
ip address 90.0.0.2 255.0.0.0 secondary
ip address 50.0.0.2 255.0.0.0
load-interval 30
speed 100
full-duplex
no cdp enable
!
interface ATM0/2
no ip address
no atm ilmi-keepalive
clock rate aal5 8000000
!
interface ATM0/2.1 point-to-point
ip address 7.0.0.1 255.0.0.0
pvc 2/100
vbr-nrt 4608 4200
!
!
interface ATM1/0
no ip address
load-interval 30
no atm ilmi-keepalive
clock rate aal5 5300000
!
interface ATM1/0.1 point-to-point
ip address 8.0.0.1 255.0.0.0
pvc 2/100
vbr-nrt 4608 4608
!
!
interface FastEthernet1/0
no ip address
shutdown
duplex auto
speed auto
no cdp enable
!
interface FastEthernet1/1
no ip address
shutdown
duplex auto
speed auto
no cdp enable
!
ip default-gateway 172.19.163.44
ip classless
ip route 60.0.0.0 255.0.0.0 ATM1/0.1
ip route 80.0.0.0 255.0.0.0 ATM0/1.1
ip route 223.255.254.254 255.255.255.255 FastEthernet0/0
ip route 223.255.254.254 255.255.255.255 1.3.0.1
ip http server
!
!
access-list 101 permit ip host 20.0.0.2 host 20.0.0.1
snmp-server community public RO
snmp-server enable traps tty
no cdp run
!
!
!
control-plane
!
!
!
!
!
!
!
alias exec c conf t
!
line con 0
exec-timeout 0 0
privilege level 15
line aux 0
line vty 0 4
exec-timeout 0 0
privilege level 15
no login
!
end
Troubleshooting TasksThe following commands verify hardware on the router:
and one of the following lines:
Router# show controllers atm
0
/
0
Interface: ATM0/0, Hardware: DSLSAR, State: up
IDB: 645F4B98 Instance: 645F646C reg_dslsar:3C200000 wic_regs: 3C200080
PHY Inst:0 Ser0Inst: 645DFC8C Ser1Inst: 645EA608 us_bwidth:4608
Slot: 0 Unit: 0 Subunit: 0 pkt Size: 4528
VCperVP: 256 max_vp: 256 max_vc: 65536 total vc: 1
rct_size:65536 vpivcibit:16 connTblVCI:8 vpi_bits: 8
vpvc_sel:3 enabled: 0 throttled: 0 cell drops: 0
Last Peridic Timer 00:44:26.872(2666872)
Parallel reads to TCQ:0 tx count reset = 0, periodic safe start = 0
Attempts to overwrite SCC txring: 0
Host Controller lockup recovery Info:
recovery count1= 0, recovery count2= 0
Saved Host Controller Info to check any lockup:
scc = 0, output_qcount = 0, head:0,
buf addr = 0x00000000, serial outputs = 0
scc = 1, output_qcount = 0, head:54,
buf addr = 0x00000000, serial outputs = 212
Serial idb(AAL5) output_qcount:0 max:40
Serial idb(RAW) output_qcount:0, max:40
Sar ctrl queue: max depth = 0, current queue depth = 0, drops = 0, urun
cnt = 0, total cnt = 106
Serial idb tx count: AAL5: 0, RAW: 212, Drop count:AAL5: 0, RAW: 0
Host Controller Clock rate Info:
SCC Clockrates:
SCC0 = 1000000 (ATM0/0)
SCC1 = 8000000 (ATM0/0)
SCC2 = 1000000 (ATM0/1)
SCC3 = 1000000 (ATM0/2)
SCC4 = 5300000 (ATM0/1)
SCC5 = 8000000 (ATM0/2)
SCC6 = 0
SCC7 = 0
WIC Register Value Notes
--------------- ---------- ----------
FPGA Dev ID (LB) 0x53 'S'
FPGA Dev ID (UB) 0x4E 'N'
FPGA Revision 0xA7
WIC Config Reg 0x35 WIC / VIC select = WIC;
CTRLE addr bit 8 = 0;
NTR Enable = 0;
OK LED on;
LOOPBACK LED off;
CD LED on;
WIC Config Reg2 0x07 Gen bus error on bad G.SHDSL ATM/T1/E1 access
Int 0 Enable Reg 0x01 G.SHDSL ATM/T1/E1 normal interrupt enabled
G.SHDSL ATM/T1/E1 error interrupt disabled
DSLSAR Register Value Notes
--------------- ---------- ----------
sdram_refresh: 0x410FFFF Expected value: 0x428xxxx
intr_event_reg: 0xC0 TMR.
intr_enable_reg: 0x13C FIFOF.FBQE.RQAF.RPQAF.TSQAF.
config: 0x660D0A20 UTOPIA.RXEN.RegulateXmit.RMCell.TXEN.
Rx Buffer size: 8192. RCT: Large, VPI Bits: 8.
status: 0x0
clkPerCell: 814121 (line rate: 4608 Kbps)
Pre-timer Count: 461
rcid_tableBase: 0x0
rct_base: 0x10000
tstBase1: 0x13C28 TST boot jump.
rawCellBase: 0x14300 (0/128) slots used.
rpq_base: 0x16000
tsqb(Tx Stat Q): 0x17000
fbq_base: 0x17880 (fbq_count: 128)
txChanQueue: 0x18000
rxBuffers: 0x30000
txBuffers: 0x130000
Lookup Error cnt: 0x0
Invalid Cell cnt: 0x0
SCCA Rx Errors: 0x0
SCCB Rx Errors: 0x0
Drop Pkt Count: 0x0
Total Tx Count: 0x0
Total Rx Count: 0x0
Timer: 0x73A141
DSLSAR Interrupts:0x0
Last Addr:0x12E14
Router# show controllers dsl
0
/
0
DSL 0/0 controller UP
Globespan xDSL controller chipset
DSL mode: SHDSL Annex B
Frame mode: Utopia
Configured Line rate: 4608Kbps
Line Re-activated 5 times after system bootup
LOSW Defect alarm: ACTIVE
CRC per second alarm: ACTIVE
Line termination: CO
FPGA Revision: 0xA7
Line 0 statistics
Current 15 min CRC: 679
Current 15 min LOSW Defect: 8
Current 15 min ES: 5
Current 15 min SES: 5
Current 15 min UAS: 441
Previous 15 min CRC: 0
Previous 15 min LOSW Defect: 0
Previous 15 min ES: 0
Previous 15 min SES: 0
Previous 15 min UAS: 0
Line 1 statistics
Current 15 min CRC: 577
Current 15 min LOSW Defect: 8
Current 15 min ES: 7
Current 15 min SES: 4
Current 15 min UAS: 455
Previous 15 min CRC: 0
Previous 15 min LOSW Defect: 0
Previous 15 min ES: 0
Previous 15 min SES: 0
Previous 15 min UAS: 0
Line-0 status
Chipset Version: 1
Firmware Version: A29733
Modem Status: Data, Status 1
Last Fail Mode: No Failure status:0x0
Line rate: 2312 Kbps
Framer Sync Status: In Sync
Rcv Clock Status: In the Range
Loop Attenuation: 0.600 dB
Transmit Power: 8.5 dB
Receiver Gain: 21.420 dB
SNR Sampling: 39.3690 dB
Line-1 status
Chipset Version: 1
Firmware Version: A29733
Modem Status: Data, Status 1
Last Fail Mode: No Failure status:0x0
Line rate: 2312 Kbps
Framer Sync Status: In Sync
Rcv Clock Status: In the Range
Loop Attenuation: 0.4294966256 dB
Transmit Power: 8.5 dB
Receiver Gain: 21.420 dB
SNR Sampling: 39.1570 dB
Dying Gasp: Present
Router# debug xdsl application
xDSL application debugging is on
Router#
Apr 23 06:01:26.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:27.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:27.720: DSL 0/0 process_get_wakeup
Apr 23 06:01:27.720: DSL 0/0 xdsl_process_boolean_events
XDSL_LINE_UP_EVENT:
Apr 23 06:01:28.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:29.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:30.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:31.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:32.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:33.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:34.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:34.476: DSL 0/0 SNR Sampling: 42.8370 dB
Apr 23 06:01:35.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:35.476: DSL 0/0 SNR Sampling: 41.9650 dB
Apr 23 06:01:36.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:36.476: DSL 0/0 SNR Sampling: 41.2400 dB
Apr 23 06:01:37.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:37.476: DSL 0/0 SNR Sampling: 40.6180 dB
Apr 23 06:01:37.476: DSL 0/0 xdsl_background_process: one_second_timer triggers download
Apr 23 06:01:37.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:37.476: DSL 0/0 xdsl_background_process:Download boolean event received
Apr 23 06:01:37.476: DSL 0/0 xdsl_controller_reset: cdb-state=down
Apr 23 06:01:37.476: %CONTROLLER-5-UPDOWN: Controller DSL 0/0, changed state to down
Apr 23 06:01:38.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:39.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:40.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:41.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:42.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:43.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:44.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:45.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:46.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:47.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:48.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:49.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:50.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:51.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:52.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:53.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:54.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:55.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:56.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:57.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:57.796: DSL 0/0 process_get_wakeup
Apr 23 06:01:57.796: DSL 0/0 xdsl_process_boolean_events
XDSL_LINE_UP_EVENT:
Apr 23 06:01:57.812: DSL 0/0 process_get_wakeup
Apr 23 06:01:57.812: DSL 0/0 xdsl_background_process: XDSL link up boolean event received
Apr 23 06:01:57.812: DSL 0/0 controller Link up! line rate: 4608 Kbps
Apr 23 06:01:57.812: DSL 0/0 xdsl_controller_reset: cdb-state=up
Apr 23 06:01:57.812: %CONTROLLER-5-UPDOWN: Controller DSL 0/0, changed state to up
Apr 23 06:01:57.812: DSL 0/0
Apr 23 06:01:57.812: Dslsar data rate 4608
Apr 23 06:01:57.816: DSL 0/0 TipRing 1, Xmit_Power Val 85, xmit_power 8.5
Apr 23 06:01:57.816: DSL 0/0 Mode 2, BW 4608, power_base_value 145, power_backoff 6
Apr 23 06:01:57.912: DSL 0/0 process_get_wakeup
Apr 23 06:01:57.916: DSL 0/0 process_get_wakeup
Apr 23 06:01:57.916: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:01:58.008: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.008: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.012: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.012: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:01:58.104: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.104: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.108: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.108: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:01:58.200: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.204: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.204: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.204: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:01:58.208: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.296: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.392: DSL 0/0 process_get_wakeup
Apr 23 06:01:58.476: DSL 0/0 process_get_wakeup
Apr 23 06:01:59.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:00.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:01.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:02.476: DSL 0/0 process_get_wakeup
Router#
Router#
Apr 23 06:02:02.920: DSL 0/0 process_get_wakeup
Apr 23 06:02:02.920: DSL 0/0 process_get_wakeup
Apr 23 06:02:02.920: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:02:03.016: DSL 0/0 process_get_wakeup
Apr 23 06:02:03.016: DSL 0/0 process_get_wakeup
Apr 23 06:02:03.016: DSL 0/0 process_get_wakeup
Apr 23 06:02:03.016: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:02:03.020: DSL 0/0 process_get_wakeup
Apr 23 06:02:03.112: DSL 0/0 process_get_wakeup
Apr 23 06:02:03.208: DSL 0/0 process_get_wakeup
Apr 23 06:02:03.304: DSL 0/0 process_get_wakeup
Apr 23 06:02:03.476: DSL 0/0 process_get_wakeup
Router#
Router#
Apr 23 06:02:04.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:04.476: DSL 0/0 SNR Sampling: 42.3790 dB
Apr 23 06:02:04.476: DSL 0/0 SNR Sampling: 42.8370 dB
Router#
Apr 23 06:02:04.476: %LINK-3-UPDOWN: Interface ATM0/0, changed state to up
Apr 23 06:02:05.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:05.476: DSL 0/0 SNR Sampling: 41.5880 dB
Apr 23 06:02:05.476: DSL 0/0 SNR Sampling: 42.3790 dB
Apr 23 06:02:05.476: %LINEPROTO-5-UPDOWN: Line protocol on Interface ATM0/0, changed state to up
Router#
Router#
Apr 23 06:02:06.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:06.476: DSL 0/0 SNR Sampling: 40.9180 dB
Apr 23 06:02:06.476: DSL 0/0 SNR Sampling: 41.5880 dB
Apr 23 06:02:07.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:07.476: DSL 0/0 SNR Sampling: 40.6180 dB
Apr 23 06:02:07.476: DSL 0/0 SNR Sampling: 41.2400 dBu all
Apr 23 06:02:07.912: DSL 0/0 process_get_wakeup
Apr 23 06:02:07.912: DSL 0/0 process_get_wakeup
Apr 23 06:02:07.912: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:02:08.008: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.008: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.008: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.008: DSL 0/0 xdsl_background_process: EOC boolean event received
Apr 23 06:02:08.016: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.104: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.200: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.296: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:08.476: DSL 0/0
All possible debugging has been turned off
Router#
Router#
Router#
Router# SNR Sampling: 40.750 dB
Apr 23 06:02:08.476: DSL 0/0 SNR Sampling: 40.6180 dB
Apr 23 06:02:09.476: DSL 0/0 process_get_wakeup
Apr 23 06:02:09.476: DSL 0/0 SNR Sampling: 39.5920 dB
Apr 23 06:02:09.476: DSL 0/0 SNR Sampling: 40.3380 dB
Router# debug xdsl driver
xDSL driver debugging is on
Router#
01:04:18: DSL 2/0 framer intr_status 0xC4
01:04:18: DSL 2/0 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/1 framer intr_status 0xC4
01:04:18: DSL 2/0 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 0/1 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/1 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 0/2 framer intr_status 0xC4
01:04:18: DSL 0/2 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/2 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 2/0 framer intr_status 0xC4
01:04:18: DSL 2/0 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/1 framer intr_status 0xC4
01:04:18: DSL 2/0 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 0/1 framer intr_status 0xC1
01:04:18: DSL 0/1 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/1 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 2/0 framer intr_status 0xC4
01:04:18: DSL 2/0 framer intr_status 0xC1
01:04:18: DSL 2/0 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/1 framer intr_status 0xC4
01:04:18: DSL 2/0 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 0/1 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/1 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 0/2 framer intr_status 0xC4
01:04:18: DSL 0/2 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/2
01:04:18: DSL 0/2 framer intr_status 0xC1 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 0/2 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/2 xdsl_gsi_int_disable(false):: 0x1
01:04:18: DSL 0/2 framer intr_status 0xC4
01:04:18: DSL 0/2 xdsl_gsi_int_disable(true):: 0x0
01:04:18: DSL 0/2 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 0/1 framer intr_status 0xC1
01:04:19: DSL 0/1 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 0/1 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 2/0 framer intr_status 0xC1
01:04:19: DSL 2/0 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 2/0 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 0/2 framer intr_status 0xC1
01:04:19: DSL 0/2 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 0/2 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 0/1 framer intr_status 0xC1
01:04:19: DSL 0/1 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 0/1 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 2/0 framer intr_status 0xC1
01:04:19: DSL 2/0 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 2/0 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 0/2 framer intr_status 0xC1
01:04:19: DSL 0/2 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 0/2 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 0/1 framer intr_status 0xC1
01:04:19: DSL 0/1 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 0/1 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 2/0 framer intr_status 0xC1
01:04:19: DSL 2/0 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 2/0 xdsl_gsi_int_disable(false):: 0x1
01:04:19: DSL 0/2 framer intr_status 0xC1
01:04:19: DSL 0/2 xdsl_gsi_int_disable(true):: 0x0
01:04:19: DSL 0/2 xdsl_gsi_int_disable(false):: 0x1
01:04:22: DSL 0/0 dsp interrupt-download next block for line-0
01:04:22: DSL 0/0 framer intr_status 0xC0
01:04:22: DSL 0/0 dsp interrupt-download next block for line-1
01:04:22: DSL 0/0 framer intr_status 0xC0
01:04:22: DSL 0/0 dsp interrupt-download next block for line-0
01:04:22: DSL 0/0 framer intr_status 0xC0
01:04:22: DSL 0/0 dsp interrupt-download next block for line-1
01:04:22: DSL 0/0 framer intr_status 0xC0
01:04:23: DSL 0/0 dsp interrupt-download next block for line-0
01:04:23: DSL 0/0 DSP interrupt disabled
01:04:23: DSL 0/0 Download completed for line-0
01:04:23: DSL 0/0 framer intr_status 0xC0
01:04:23: DSL 0/0 dsp interrupt-download next block for line-1
01:04:23: DSL 0/0 DSP interrupt disabled
01:04:23: DSL 0/0 Download completed for line-1
01:04:23: DSL 0/0 Framer interrupt enabled
01:04:23: DSL 0/0 framer intr_status 0xC0
01:04:23: DSL 0/0 controller Link up! line rate: 4608 Kbps
01:04:23: %CONTROLLER-5-UPDOWN: Controller DSL 0/0, changed state to up
01:04:23: DSL 0/0 framer intr_status 0xC4
01:04:23: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
01:04:23: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
01:04:23: DSL 0/0 framer intr_status 0xC1
01:04:23: DSL 0/0 framer intr_status 0xC4
Router# debug xdsl driver
xDSL driver debugging is on
00:58:22: DSL 0/0 dsp interrupt-download next block for line-0
00:58:23: DSL 0/0 framer intr_status 0xC0
00:58:24: DSL 0/0 dsp interrupt-download next block for line-0
00:58:24: DSL 0/0 framer intr_status 0xC0
00:58:37: DSL 0/0 dsp interrupt-download next block for line-0
00:58:37: DSL 0/0 framer intr_status 0xC0
00:58:38: DSL 0/0 dsp interrupt-download next block for line-0
00:58:38: DSL 0/0 framer intr_status 0xC0
00:58:38: DSL 0/0 dsp interrupt-download next block for line-0
00:58:38: DSL 0/0 DSP interrupt disabled
00:58:38: DSL 0/0 Download completed for line-0
00:58:38: DSL 0/0 Framer interrupt enabled
00:58:38: DSL 0/0 framer intr_status 0xC0
00:58:38: DSL 0/0 controller Link up! line rate: 1600 Kbps
00:58:38: %CONTROLLER-5-UPDOWN: Controller DSL 0/0, changed state to up
00:58:38: Dslsar data rate 1600
00:58:38: DSL 0/0 framer intr_status 0xC4
00:58:38: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:58:38: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:58:38: DSL 0/0 framer intr_status 0xC4
00:58:38: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:58:38: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:58:38: DSL 0/0 framer intr_status 0xC1
00:58:38: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:58:38: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:58:38: DSL 0/0 framer intr_status 0xC4
00:58:38: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:58:38: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:58:38: DSL 0/0 framer intr_status 0xC1
00:58:38: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
Router# debug xdsl driver
xDSL driver debugging is on
00:55:15: DSL 0/0 dsp interrupt-download next block for line-1
00:55:15: DSL 0/0 framer intr_status 0xC0
00:55:16: DSL 0/0 dsp interrupt-download next block for line-1
00:55:16: DSL 0/0 framer intr_status 0xC0
00:55:17: DSL 0/0 dsp interrupt-download next block for line-1
00:55:17: DSL 0/0 framer intr_status 0xC0
00:55:19: DSL 0/0 dsp interrupt-download next block for line-1
00:55:19: DSL 0/0 framer intr_status 0xC0
00:55:32: DSL 0/0 dsp interrupt-download next block for line-1
00:55:32: DSL 0/0 framer intr_status 0xC0
00:55:32: DSL 0/0 dsp interrupt-download next block for line-1
00:55:32: DSL 0/0 framer intr_status 0xC0
00:55:32: DSL 0/0 dsp interrupt-download next block for line-1
00:55:32: DSL 0/0 DSP interrupt disabled
00:55:32: DSL 0/0 Download completed for line-1
00:55:32: DSL 0/0 Framer interrupt enabled
00:55:32: DSL 0/0 framer intr_status 0xC0
00:55:32: DSL 0/0 controller Link up! line rate: 1600 Kbps
00:55:32: %CONTROLLER-5-UPDOWN: Controller DSL 0/0, changed state to up
00:55:32: Dslsar data rate 1600
00:55:46: %LINK-3-UPDOWN: Interface ATM0/0, changed state to up
00:55:47: %LINEPROTO-5-UPDOWN: Line protocol on Interface ATM0/0, changed state to up
00:56:28: DSL 0/0 framer intr_status 0xC8
00:56:28: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:56:28: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:56:28: DSL 0/0 framer intr_status 0xC8
00:56:28: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:56:28: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:56:28: DSL 0/0 framer intr_status 0xC2
00:56:28: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:56:28: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:56:33: DSL 0/0 framer intr_status 0xC8
00:56:33: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:56:33: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:56:33: DSL 0/0 framer intr_status 0xC2
00:56:33: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:56:33: DSL 0/0
00:56:33: DSL 0/0 framer intr_status 0xC8 xdsl_gsi_int_disable(false):: 0x1
00:56:33: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
00:56:33: DSL 0/0 xdsl_gsi_int_disable(false):: 0x1
00:56:33: DSL 0/0 framer intr_status 0xC8
00:56:33: DSL 0/0 xdsl_gsi_int_disable(true):: 0x0
Router# debug xdsl eoc
*Jan 3 18:34:46.824: %CONTROLLER-5-UPDOWN: Controller DSL 0/0, changed state to up
*Jan 3 18:34:46.924: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:46.924: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:46.924: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:46.924: DSL 0/0: GT_FAIL
*Jan 3 18:34:46.924: eoc_get_message for line::0
*Jan 3 18:34:46.924: Rx EOC remove transparency:: 1F 1 0 46 10
*Jan 3 18:34:46.928: data_transparency_remove: Done, eoc packet size = 5
*Jan 3 18:34:46.928: Good eoc packet received
*Jan 3 18:34:46.928: incoming request eocmsgid: 1 from line 0
*Jan 3 18:34:46.928: Tx Converted EOC message:: 21 81 1 43 43 49 53 43 4F 0 0 0 2 1 0 E9 61
*Jan 3 18:34:46.932: data_transparency_add: eoc packet size - before 17, after 17
*Jan 3 18:34:47.020: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:47.020: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:47.020: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:47.020: DSL 0/0: GT_FAIL
*Jan 3 18:34:47.020: eoc_get_message for line::0
*Jan 3 18:34:47.020: Rx EOC remove transparency:: 12 2 74 8A
*Jan 3 18:34:47.024: data_transparency_remove: Done, eoc packet size = 4
*Jan 3 18:34:47.024: Good eoc packet received
*Jan 3 18:34:47.024: incoming request eocmsgid: 2 from line 0
*Jan 3 18:34:47.024: Tx Converted EOC message:: 21 82 1 0 0 0 0 0 52 33 2E 30 2E 31 43 4E 53 38 44 44 30 41 41 41 43 43 49 53 43 4F 0 0 0 57 49 43 2D 53 48 44 53 4C 2D 56 32 46 4F 43 30 38 33 37 35 55 41 4C 0 31 32 2E 34 28 33 2E 35 2E 31 29 0 66 74
*Jan 3 18:34:47.044: data_transparency_add: eoc packet size - before 71, after 71
*Jan 3 18:34:47.116: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:47.116: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:47.116: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:47.116: DSL 0/0: GT_FAIL
*Jan 3 18:34:47.116: eoc_get_message for line::0
*Jan 3 18:34:47.116: Rx EOC remove transparency:: 12 3 0 0 6D E9
*Jan 3 18:34:47.120: data_transparency_remove: Done, eoc packet size = 6
*Jan 3 18:34:47.120: Good eoc packet received
*Jan 3 18:34:47.120: incoming request eocmsgid: 3 from line 0
*Jan 3 18:34:47.120: Tx Converted EOC message:: 21 83 0 0 0 1 AC
*Jan 3 18:34:47.120: data_transparency_add: eoc packet size - before 7, after 7
GSI Tx buffer yet to transmit
*Jan 3 18:34:47.212: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:47.212: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:47.212: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:47.212: DSL 0/0: GT_FAIL
*Jan 3 18:34:47.212: eoc_get_message for line::0
*Jan 3 18:34:47.212: Rx EOC remove transparency:: 12 5 0 0 0 E9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 42
*Jan 3 18:34:47.216: data_transparency_remove: Done, eoc packet size = 24
*Jan 3 18:34:47.216: Good eoc packet received
*Jan 3 18:34:47.216: incoming request eocmsgid: 5 from line 0
*Jan 3 18:34:47.220: Tx Converted EOC message:: 21 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1E AB
*Jan 3 18:34:47.224: data_transparency_add: eoc packet size - before 26, after 26
GSI Tx buffer yet to transmit
GSI Tx buffer yet to transmit
*Jan 3 18:34:47.224: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:47.224: DSL 0/0: Current length 40 GTI_EOM
*Jan 3 18:34:47.224: DSL 0/0: GT_FAIL
*Jan 3 18:34:51.824: xdsl_background_process:
*Jan 3 18:34:51.824: sending request eocmsgid: 12
*Jan 3 18:34:51.824: Tx Converted EOC message:: 21 C C0 FF
*Jan 3 18:34:51.824: data_transparency_add: eoc packet size - before 4, after 4
*Jan 3 18:34:51.824: size of eoc full status request :: 2
*Jan 3 18:34:51.928: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:51.928: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:51.928: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:51.928: DSL 0/0: GT_FAIL
*Jan 3 18:34:51.928: eoc_get_message for line::0
*Jan 3 18:34:51.928: Rx EOC remove transparency:: 12 C A 63
*Jan 3 18:34:51.932: data_transparency_remove: Done, eoc packet size = 4
*Jan 3 18:34:51.932: Good eoc packet received
*Jan 3 18:34:51.932: incoming request eocmsgid: 12 from line 0
*Jan 3 18:34:51.932: Tx Converted EOC message:: 21 8C 0 F D3 1 0 0 5 2 46 5 1 44 59
*Jan 3 18:34:51.932: data_transparency_add: eoc packet size - before 15, after 15
*Jan 3 18:34:51.936: size of eoc status response :: 13
*Jan 3 18:34:51.936: Tx Converted EOC message:: 21 8C 0 10 D3 1 0 0 6 1 46 5 2 50 2C
*Jan 3 18:34:51.936: data_transparency_add: eoc packet size - before 15, after 15
*Jan 3 18:34:51.936: size of eoc status response :: 13
*Jan 3 18:34:51.940: Tx Converted EOC message:: 21 89 4 DB 82
*Jan 3 18:34:51.940: data_transparency_add: eoc packet size - before 5, after 5
*Jan 3 18:34:51.940: size of eoc status response :: 3GSI Tx buffer yet to transmit
GSI Tx buffer yet to transmit
*Jan 3 18:34:52.024: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:52.024: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:52.024: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:52.024: DSL 0/0: GT_FAIL
*Jan 3 18:34:52.024: eoc_get_message for line::0
*Jan 3 18:34:52.024: Rx EOC remove transparency:: 12 11 6E A8
*Jan 3 18:34:52.024: data_transparency_remove: Done, eoc packet size = 4
*Jan 3 18:34:52.028: Good eoc packet received
*Jan 3 18:34:52.028: incoming request eocmsgid: 17 from line 0
*Jan 3 18:34:52.028: Tx Converted EOC message:: 21 91 0 0 0 D6 56
*Jan 3 18:34:52.028: data_transparency_add: eoc packet size - before 7, after 7
*Jan 3 18:34:52.028: size of eoc status response :: 5GSI Tx buffer yet to transmit
GSI Tx buffer yet to transmit
*Jan 3 18:34:52.120: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:52.120: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:52.120: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:52.120: DSL 0/0: GT_FAIL
*Jan 3 18:34:52.120: eoc_get_message for line::0
*Jan 3 18:34:52.120: Rx EOC remove transparency:: 12 8C 0 3 0 B 7 5 D8 4 5F 6 1 27 64
*Jan 3 18:34:52.124: data_transparency_remove: Done, eoc packet size = 15
*Jan 3 18:34:52.124: Good eoc packet received
*Jan 3 18:34:52.216: DSL 0/0: line 0 EOC Rcv Intr :: 0x4
*Jan 3 18:34:52.216: DSL 0/0:Current length 40 GTI_OK
*Jan 3 18:34:52.216: DSL 0/0:msg rcvd line 0
*Jan 3 18:34:52.216: DSL 0/0: GT_FAIL
*Jan 3 18:34:52.216: eoc_get_message for line::0
*Jan 3 18:34:52.216: Rx EOC remove transparency:: 12 8C 0 5 0 3 0 0 12 3 2 26 2 1C 4F
*Jan 3 18:34:52.220: data_transparency_remove: Done, eoc packet size = 15
Router# debug xdsl error
xDSL error debugging is on
Router#
Configuration Examples for ATM Mode for Two-Wire or Four-Wire SHDSLRouter A CPE Configuration Examplecontroller DSL 1/2 mode atm line-term cpe line-mode 2-wire line-zero dsl-mode shdsl symmetric annex B ! ! ! ! connect hp DSL 1/0 0 DSL 1/2 0 ! ! Router B CO Configuration ExampleCurrent configuration : 3183 bytes ! version 12.3 service timestamps debug uptime service timestamps log uptime no service password-encryption ! hostname 3725 ! boot-start-marker boot system flash c3725-is-mz.0424 boot system tftp shriv/c3725-is-mz.new 223.255.254.254 boot-end-marker ! ! memory-size iomem 25 no network-clock-participate slot 1 no network-clock-participate slot 2 no network-clock-participate wic 0 no network-clock-participate wic 1 no network-clock-participate wic 2 no network-clock-participate aim 0 no network-clock-participate aim 1 no aaa new-model ip subnet-zero ip cef ! ! ! ! ! ! ! controller DSL 0/0 mode atm line-term co line-mode 4-wire enhanced dsl-mode shdsl symmetric annex B line-rate 4608 ! controller DSL 0/1 mode atm line-term co line-mode 4-wire enhanced dsl-mode shdsl symmetric annex B line-rate 4608 controller DSL 0/2 mode atm line-term co line-mode 4-wire enhanced dsl-mode shdsl symmetric annex B line-rate 4608 ! controller DSL 1/0 mode atm line-term co line-mode 4-wire enhanced dsl-mode shdsl symmetric annex B line-rate 4608 ! ! ! interface ATM0/0 no ip address load-interval 30 no atm ilmi-keepalive clock rate aal5 8000000 ! interface ATM0/0.1 point-to-point ip address 5.0.0.1 255.0.0.0 pvc 2/100 vbr-rt 2000 2000 oam-pvc 0 encapsulation aal5mux ip ! ! interface FastEthernet0/0 ip address 1.3.208.25 255.255.0.0 duplex auto speed auto no cdp enable ! interface ATM0/1 no ip address load-interval 30 no atm ilmi-keepalive clock rate aal5 5300000 ! interface ATM0/1.1 point-to-point ip address 6.0.0.1 255.0.0.0 pvc 2/100 cbr 4608 ! ! interface FastEthernet0/1 mac-address 0000.0000.0011 ip address 70.0.0.2 255.0.0.0 secondary ip address 90.0.0.2 255.0.0.0 secondary ip address 50.0.0.2 255.0.0.0 load-interval 30 speed 100 full-duplex no cdp enable ! interface ATM0/2 no ip address no atm ilmi-keepalive clock rate aal5 8000000 ! interface ATM0/2.1 point-to-point ip address 7.0.0.1 255.0.0.0 pvc 2/100 vbr-nrt 4608 4200 ! ! interface ATM1/0 no ip address load-interval 30 no atm ilmi-keepalive clock rate aal5 5300000 ! interface ATM1/0.1 point-to-point ip address 8.0.0.1 255.0.0.0 pvc 2/100 vbr-nrt 4608 4608 ! ! interface FastEthernet1/0 no ip address shutdown duplex auto speed auto no cdp enable ! interface FastEthernet1/1 no ip address shutdown duplex auto speed auto no cdp enable ! ip default-gateway 172.19.163.44 ip classless ip route 60.0.0.0 255.0.0.0 ATM1/0.1 ip route 80.0.0.0 255.0.0.0 ATM0/1.1 ip route 223.255.254.254 255.255.255.255 FastEthernet0/0 ip route 223.255.254.254 255.255.255.255 1.3.0.1 ip http server ! ! access-list 101 permit ip host 20.0.0.2 host 20.0.0.1 snmp-server community public RO snmp-server enable traps tty no cdp run ! ! ! control-plane ! ! ! ! ! ! ! alias exec c conf t ! line con 0 exec-timeout 0 0 privilege level 15 line aux 0 line vty 0 4 exec-timeout 0 0 privilege level 15 no login ! end Additional ReferencesFor additional information related to the ATM Mode for Two-Wire or Four-Wire SHDSL feature, refer to the following references. Related Documents
MIBsTechnical AssistanceFeature Information for ATM Mode for Two-Wire or Four-Wire SHDSLThe following table provides release information about the feature or features described in this module. This table lists only the software release that introduced support for a given feature in a given software release train. Unless noted otherwise, subsequent releases of that software release train also support that feature. Use Cisco Feature Navigator to find information about platform support and Cisco software image support. To access Cisco Feature Navigator, go to www.cisco.com/go/cfn. An account on Cisco.com is not required.
GlossaryABR--available bit rate. An ATM service type in which the ATM network makes a "best effort" to meet the transmitter's bandwidth requirements. ABR uses a congestion feedback mechanism that allows the ATM network to notify the transmitters that they should reduce their rate of data transmission until the congestion decreases. Thus, ABR offers a qualitative guarantee that the transmitter's data can get to the intended receivers without unwanted cell loss. ATM--Asynchronous Transfer Mode. A form of digitized data transmission based on fixed-length cells that can carry data, voice, and video at high speeds. CBR--constant bit rate. A data transmission that can be represented by a nonvarying, or continuous, stream of bits or cell payloads. Applications such as voice circuits generate CBR traffic patterns. CBR is an ATM service type in which the ATM network guarantees to meet the transmitter's bandwidth and quality-of-service (QoS) requirements. CO--central office. Local telephone company office to which all local loops in a given area connect and in which circuit switching of subscriber lines occur. CPE--customer premises equipment. CPE includes devices, such as CSU/DSUs, modems, and ISDN terminal adapters, required to provide an electromagnetic termination for wide-area network circuits before connecting to the router or access server. This equipment was historically provided by the telephone company, but is now typically provided by the customer in North American markets. Downstream--Refers to the transmission of data from the central office (CO or COE) to the customer premises equipment (CPE). G.SHDSL--Multirate Symmetrical High-Speed Digital Subscriber Line. UBR--unspecified bit rate. QoS class defined by the ATM Forum for ATM networks. UBR allows any amount of data up to a specified maximum to be sent across the network, but there are no guarantees in terms of cell loss rate and delay. Compare with ABR (available bit rate), CBR, and VBR. Upstream--Refers to the transmission of data from the customer premises equipment (CPE) to the central office equipment (CO or COE). VBR--variable bit rate. QOS class defined by the ATM Forum for ATM networks. VBR is subdivided into a real time (rt) class and non-real time (nrt) class. VBR-rt--VBR-real-time is used for connections in which there is a fixed timing relationship between samples. VBR-nrt--VBR-non-real-time is used for connections in which there is no fixed timing relationship between samples, but that still need a guaranteed QoS. Compare with ABR, CBR, and UBR.
Cisco and the Cisco logo are trademarks or registered trademarks of Cisco and/or its affiliates in the U.S. and other countries. To view a list of Cisco trademarks, go to this URL: www.cisco.com/go/trademarks. Third-party trademarks mentioned are the property of their respective owners. The use of the word partner does not imply a partnership relationship between Cisco and any other company. (1110R) Any Internet Protocol (IP) addresses and phone numbers used in this document are not intended to be actual addresses and phone numbers. Any examples, command display output, network topology diagrams, and other figures included in the document are shown for illustrative purposes only. Any use of actual IP addresses or phone numbers in illustrative content is unintentional and coincidental. © 2011 Cisco Systems, Inc. All rights reserved.
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