The ME 3800X and ME 3600X switches support Synchronous Ethernet (SyncE), which is the PHY-layer frequency-synchronization solution for IEEE 802.3 links. It is an evolution of the conventional Ethernet and Ethernet + SDH and SONET-based synchronization. SyncE is used to synchronize and send clock information to remote sites on the network. Each network element along the synchronization path must support SyncE. SyncE provides only frequency synchronization, not related to time or space.
SyncE provides a method to synchronize the Ethernet network by having all Ethernet ports send data based on a reference clock. All devices supporting SyncE must send and receive data in cycles of fixed size and duration. The data size depends on the Ethernet speed. The rate of transmission is 8000 cycles per second. Each device must be able to support a system timing master, which is the synchronization source. A sync port is the port on which synchronization information is received. All SyncE frames coming from the sync port are the source of synchronization for all other ports on the device.
The switch 10 Gigabit Ethernet uplink ports or BITS interface support line clock recovery, sending and receiving clock information. Downlink ports do not perform clock recovery and can only send clock signals.
The switch supports TI (1544 kilobits/s) and E1 (2048 kb/s or 2048 KHz) clock timing synchronization.
A switch comes up in a free-run state, using the internal oscillator (Stratum 3) for synchronization. If there is a valid clock reference with a set priority, the switch locks to that reference. If there is no reliable clock source available, the switch remains in free-run mode. If the current clock becomes invalid, the switch goes into holdover mode and replays the saved clock from the last source. The switch SyncE LEDs show the status of the internal clock: locked (green), free run (off), or in a holdover state (amber).
The reference clock source can be:
A Building Integrated Timing Supply (BITS) clock input
A PHY-recovered clock from uplink ports. The ME 3800X and 3600X switch supports a PHY-recovered clock only from the small form-factor pluggable (SFP+) uplink ports with 10 Gigabit SFP+ or 1000BASE-X fiber SFP modules.
All uplink and downlink ports transmit data on the same reference clock.
The switch monitors each input clock for frequency accuracy and activity. An input clock with a frequency out-of-band alarm or an activity alarm is invalid. Invalid clocks are not selected as the reference clock.
During normal operation, the reference clock is selected based on an algorithm that uses the priority rankings that you assign to the input clocks by using the network-clock input-source priority global configuration command. Priority 1 is the highest, and priority 15 is the lowest. If you try to assign the same priority to more than one clock, error message appears. Unused input clocks are given a priority value of 0, which disables the clocks and makes them unavailable for selection. The clock selection is based on signal failure, priority, and manual configuration. If you have not manually configured a reference clock, the algorithm selects the clock with the highest priority that does not experience signal failure.
With this configuration, pure priority-based mode, an intermittent failure or changes in the network topology can cause timing loops or a loss of connectivity with the clock reference. The Ethernet Synchronous Messaging Channel (ESMC) with Synchronization Status Messages (SSM) provides a way to implement quality in synchronous networks.
Reference clocks operate in revertive or nonrevertive mode, configured by using the network-clock revertive global configuration command. The reverence clocks will be in non-revertive mode by default.
In revertive mode, if an input clock with a higher priority than the selected reference becomes available, the higher priority reference is immediately selected.
In nonrevertive mode, if a new input clock with a higher priority becomes available, the higher-priority clock is selected. This means, among all available input reference clocks, the higher-priority clock is selected.
In non revertive mode, when an input clock with a high priority present on the system becomes invalid or unavailable, a lower priority clock will be selected. However when the higher priority clock becomes available again it will not be selected.
Note In revertive mode of operation, when the lost high priority reference becomes available again, it is selected. However, in non-revertive mode of operation, the regained high priority reference is not selected.
You can use the network-clock switch privileged EXEC command to configure the input reference to be either forced or automatically selected by the selection algorithm based on the highest priority valid input clock. In revertive mode, the forced clock automatically becomes the selected reference. In nonrevertive mode, the forced clock becomes the selected reference only when the existing reference is invalidated or unavailable.
The ME 3800X and ME 3600X switch supports a BITS interface through an RJ-45 connector. The connection can be used for sending and receiving T1 and E1 timing signals.
You can configure all Ethernet ports to send data referenced to the BITS recovered clock. The BITS signal is used as long as it does not have these faults:
loss of signal
out of frame
remote alarm indication
The switch supports BITS IN and BITS OUT, and recovers and sends BITS timing, T1, E1. The switch does not support T1 or E1 data transmission. You can configure the BITS interface input and output, including line coding and line buildout (output). You can also shut down the BITS controller.
The switch supports these BITS configurations:
– 2048 KHz
– Framing mode: FAS, MFAS, FASCRC4, MFASCRC4 with line coding: AMI, HDB3
– Framing mode: D4 and ESF
– Line coding: AMI, B8ZS
– Line buildout (output): 0 to 133 feet, 133 to 266 feet, 266 to 399 feet, 399 to 533 feet, or 533 to 655 feet
Synchronous Ethernet and Ethernet Synchronization Messaging Channel
The ME3600/ME3800 switches support the following Synchronous Ethernet (SyncE) and Ethernet Synchronization Messaging Channel (ESMC) features:
Common IOS CLI configuration
Configuration on all ports, including BITS ports and copper ports
Can be enabled or disabled on individual ports
Synchronous Ethernet clock derived from user configuration
Synchronous Status Message (SSM) on BITS interface
Ethernet Synchronous Messaging Channel (ESMC) on all Ethernet ports
Clock selection is configured by the user based on clock priority and ESMC/SSM messages received from all sources and ports.
A Synchronous Status Message (SSM) informs the peer about the quality of the local clock source and is used to detect and avoid timing loops. SSMs are transported over the Ethernet Synchronization Messaging Channel (ESMC). All SSM information transported over Ethernet ports must be in the ESMC message format (G.8264).
The BITS port can be configured as a T1 or E1 interface.
For T1s, SSM messages are transported over the 4 Kbps datalink channel.
For E1s, SSM messages are transported over the E1 signaling channel.
To configure synchronous ethernet in Release 15.1(2)EY
The controller BITS CLIs should be used to configure shutdown, linecode and line-build-out as these options are missing in netsync PI infrastructure CLIs. Once the netsync infrastructure CLIs implement these configuration options, the platform "controller BITS" CLIs will be deprecated.