This chapter provides an overview of the release history, supported features, restrictions, and Management Information Base (MIB) support for the serial SPAs on the Cisco ASR 1000 Series Aggregation Services Routers.
The following serial SPAs were supported on the SIP-400 linecard.
Channelized TE1 SPA (Maverick)
Channelized T3 SPA (Patriot)
Channelized OC3 STM SPA (Prowler)
Clear Channel T3E3 SPA (Javelin)
All serial SPAs supported SIP-200 on Cascades release will be supported on SIP-400
Cisco IOS XE Release 3.10
Support for the 8-Port Channelized T1/E1 Serial SPA (SPA-8XCHT1/E1-V2) was introduced on the Cisco ASR 1000 Series SIPs.
Cisco IOS XE Release 3.8
Support for the 8-Port Clear-Channel T3/E3 Serial SPA (SPA-8XT3/E3) was introduced on the Cisco ASR 1000 Series SIPs.
Cisco IOS XE Release 2.6
Support for the 1-Port Channelized OC-12/STM-4 SPA was introduced on the Cisco ASR 1000 Series SIPs.
Cisco IOS XE Release 2.2
Support for the 1-Port Channelized OC-3/STM-1 SPA was introduced on the Cisco ASR 1000 Series SIPs.
Cisco IOS XE Release 2.1
Support for the following SPAs was introduced on the Cisco ASR 1000 Series SIPs:
2-Port T3/E3 Serial SPA (SPA-2XT3/E3)
4-Port T3/E3 Serial SPA (SPA-4XT3/E3)
8-Port Channelized T1/E1 Serial SPA (SPA-8XCHT1/E1)
2-Port Channelized T3 SPA(SPA-2XCT3/DS0)
4-Port Channelized T3 SPA (SPA-4XCT3/DS0)
4-Port Serial SPA (SPA-4TX-Serial)
Note There are some variations in the support provided by SPA models and software releases. These differences are described in the “Restrictions” section, and in the corresponding configuration chapter pertaining to that SPA.
The following is a list of some of the significant software features supported by the serial SPAs on the Cisco ASR 1000 Series Aggregation Services Routers:
Software selectable between T1, E1, T3, or E3 framing on each card (all the ports can be simultaneously configured as T1, E1, T3, or E3). Applies to the 2-Port and 4-Port Clear-Channel T3/E3 SPAs and the 8-Port Channelized T1/E1 SPA.
Layer 2 encapsulation support:
– Point-to-Point Protocol (PPP)
– High-level Data Link Control (HDLC)
– Frame Relay
Internal or network clock (selectable per port).
Online insertion and removal (OIR).
Hot Standby Router Protocol (HSRP).
Alarm reporting: 24-hour history maintained, 15-minute intervals on all errors.
16-bit and 32-bit cyclic redundancy checks (CRC) supported (16-bit is the default).
Local and remote loopback.
Bit error rate testing (BERT) pattern generation and detection per port.
Programmable BERT pattern enhancements.
Note The programmable BERT pattern enhancements are not supported on the 2-Port, 4-Port, and 8-Port Clear-Channel T3/E3 Serial SPAs and the 8-Port Channelized T1/E1 SPA.
Dynamic provisioning—Allows for the addition of new customer circuits within a channelized interface without affecting other customers.
Field-programmable device (FPD) upgrades.
End-to-end FRF.12 fragmentation support (Quantum Flow Processor [QFP] based).
QFP-based Multilink PPP (MLPPP) and Link Fragmentation and Interleaving (LFI).
Support for MLPPP across all SPAs.
Support for MLPPP using any combination of E1, T1, and NxDS0 member links.
Compressed Real-Time Protocol (cRTP)—8-Port Channelized T1/E1 Serial SPA and 2-Port and 4-Port Channelized T3 SPAs only.
Effective from Cisco IOS XE Release 3.9, the 8-Port Clear-Channel T3/E3 Serial SPA is supported on the Cisco ASR1000-SIP10, the Cisco ASR 1001 Router, the Cisco ASR 1002 Router, and the Cisco ASR 1002-F Router.
– All ports can be fully channelized down to DS0.
– Data rates in multiples of 56 Kbps or 64 Kbps per channel.
– Maximum 1.536 Mbps for each T1 port.
– D4 Superframe (SF) and Extended Superframe (ESF) support for each T1 port.
– ANSI T1.403 and AT&T TR54016 CI FDL support.
– Internal and receiver recovered clocking modes.
– Short haul and long haul channel service unit (CSU) support.
– Bipolar eight zero substitution (B8ZS) and alternate mark inversion (AMI) line encoding.
Note B8ZS and AMI line encoding are not configurable for TW on the 2-Port and 4-Port Channelized T3 SPA.
Note E1 is not supported on the 1-Port Channelized OC-12/STM-4 SPA in Cisco IOS XE Release 2.6.
– Maximum 1.984 Mbps for each E1 port in framed mode and a 2.048 Mbps in unframed E1 mode.
– All ports can be fully channelized down to DS0.
– Compliant with ITU G7.03, G.704, ETSI and ETS300156.
– Internal and receiver recovered clocking modes.
– Hi-density bipolar with three zones (HDB3) and AMI line encoding.
Note E3 is not supported on the 1-Port Channelized OC-12/STM-4 SPA in Cisco IOS XE Release 2.6.
– Full duplex connectivity at E3 rate (34.368 MHz).
– Supports ITU-T G.751 or G.832 framing (software selectable).
– HD3B line coding.
– Compliant with E3 pulse mask.
– Line build-out: configured for up to 450 feet (135 m) of type 728A or equivalent coaxial cable.
– Loopback modes: data terminal equipment (DTE), local, dual, and network.
– E3 alarm/event detection (once per second polling):
- Alarm indication signal (AIS)
- Loss of frame (LOF)
- Remote alarm indication (RAI)
– Subrate and scrambling features for these data service unit (DSU) vendors:
- Digital Link
- ADC Kentrox
– Binary 3-zero substitution (B3ZS) line coding.
– Compliant with DS3 pulse mask per ANSI T1.102-1993.
– DS3 far-end alarm and control (FEAC) channel support.
– Full duplex connectivity at DS3 rate (44.736 MHz).
– 672 DS0s per T3.
– Loopback modes: DTE, local, remote, dual, and network.
– C-bit or M23 framing (software selectable).
– Line build-out: configured for up to 450 feet (135 m) of type 734A or equivalent coaxial cable.
– DS3 alarm/event detection (once per second polling):
- Out of frame (OOF)
- Far-end receive failure (FERF)
– Generation and termination of DS3 Maintenance Data Link (MDL) in C-bit framing.
– Full FDL support and FDL performance monitoring.
Note FDL is not supported on the 2-Port, 4-Port, and 8-Port Clear-Channel T3/E3 SPAs. Whereas, FDL is supported on the 2-Port and 4-Port Channelized T3 SPAs, the 1-Port Channelized OC-3/STM-1 SPA, and the 1-Port Channelized OC-12/STM-4 SPA.
– Subrate and scrambling features for these DSU vendors:
– Digital Link
– ADC Kentrox
Note Mixed Port type (T3/E3) is supported on the 8-Port Clear-Channel T3/E3 SPA.
Consider the following restrictions when configuring the serial SPAs on the Cisco ASR 1000 Series Aggregation Services Routers:
Note For additional information, see also the configuration chapters for the corresponding SPA model. For other SIP-specific features and restrictions see also Chapter 3, “Overview of the SIP”.
FRF.16—Multilink Frame Relay (MLFR) is not supported.
MLPPP is only supported on serial PPP interfaces. MLPPP is not supported over Frame Relay, ATM, or PPPoE interfaces.
On a 2-Port and 4-Port Channelized T3 SPA, when one of the T3 ports is configured as a DS3 Clear-Channel interface and the other T3 ports are configured with a large number (greater than or equal to 400) of low bandwidth channels (NxDS0, N=1, 2, 3, or 4), the DS3 Clear-Channel interface is not able to run at 100 percent DS3 line rate when the low bandwidth channels are idle (when not transmitting or receiving packets). This issue does not occur if the low bandwidth channels are not idle.
The maximum number of channels supported on the channelized SPAs are:
– 1023 channels per SPA—On a 2-Port and 4-Port Channelized T3 SPA or 1-Port Channelized OC-3/STM-1 SPA.
– 2000 NxDS0 per SPA—On a 1-Port Channelized OC-12/STM-4 SPA.
On a 2-Port and 4-Port Channelized T3 SPA or 1-Port Channelized OC-3/STM-1 SPA, the maximum number of FIFO buffers is 4096. The FIFO buffers are shared among the interfaces; how they are shared is determined by speed. If all the FIFO buffers have been assigned to existing interfaces, a new interface cannot be created, and the “%Insufficient FIFOs to create channel group” error message is seen.
To find the number of available FIFO buffers, use the
show controller t3
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To verify the SPA hardware type that is installed in your Cisco ASR 1000 Series Routers, you can use the
command or the
command (once the interface has been configured). There are several other commands on the Cisco ASR 1000 Series Routers that also provide SPA hardware information.
Table 14-2 shows the hardware description that appears in the
command output for each type of SPA that is supported on the Cisco ASR 1000 Series Routers.
Table 14-2 SPA Hardware Descriptions in show Commands
Description in show interfaces and show controllers Commands
2-Port Clear-Channel T3/E3 SPA
“Hardware is SPA-2XT3/E3”
4-Port Clear-Channel T3/E3 SPA
“Hardware is SPA-4XT3/E3”
8-Port Clear-Channel T3/E3 SPA
“Hardware is SPA-8XT3/E3”
8-Port Channelized T1/E1 SPA
“Hardware is SPA-8XCHT1/E1-V2”
4-Port Serial Interface SPA
“Hardware is SPA-4XT-SERIAL”
1-Port Channelized OC-3/STM-1 SPA
“Hardware is SPA-1XCHSTM1/OC3”
1-Port Channelized OC-12/STM-4 SPA
“Hardware is SPA-1XCHOC12/DS0”
Examples of the show interfaces Command
The following example shows an output of the
show interfaces serial
command on a Cisco ASR 1000 Series Router with a 4-Port Clear-Channel T3/E3 SPA installed in slot 2:
router#: show interfaces serial 2/0/0
Serial2/0/0 is up, line protocol is up
Hardware is SPA-4XT3/E3[3/0]
MTU 4470 bytes, BW 44210 Kbit, DLY 200 usec,
reliability 248/255, txload 1/255, rxload 1/255
Encapsulation HDLC, crc 16, loopback not set
Keepalive set (10 sec)
Last input 00:00:06, output 00:00:07, output hang never
Last clearing of ''show interface'' counters 00:00:01
Input queue: 0/75/0/0 (size/max/drops/flushes); Total output drops: 0