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How to Configure Network-Wide Synchronization in WAN Switching Networks

Cisco - How to Configure Network-Wide Synchronization in WAN Switching Networks

Document ID: 4400

Updated: Apr 17, 2009

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Introduction

This document describes network-wide clock synchronization concepts for Cisco WAN Switches. It focuses on clock source selection criteria for a given node in a Cisco WAN Switching network. This document does not describe design aspects or related implementation details.

The intended audience for this document is the user who needs an introduction to clock synchronization in BPX, IPX/IGX and MGX networks or someone who wants an overview of network-wide clock synchronization. A basic understanding of BPX, IPX, IGX and MGX functionality is assumed. For answers to basic WAN Switching clock questions, refer to WAN Switching Network Synchronization Fundamentals.

Prerequisites

Requirements

There are no specific requirements for this document.

The information presented in this document was created from devices in a specific lab environment. All of the devices used in this document started with a cleared (default) configuration. If you are working in a live network, ensure that you understand the potential impact of any command before using it.

Components Used

The configurations provided in this document were developed and tested using the latest generally available (GA) software versions on the Cisco BPX 8600, IGX 8400, MGX 8220 and MGX 8800 series equipment.

Conventions

For more information on document conventions, refer to the Cisco Technical Tips Conventions.

Clocking Concepts

Network-Wide Clock Synchronization

The primary goal of network-wide clock synchronization is to make each node in a network synchronize to the highest, closest stratum clock source available. Network-wide clock synchronization takes into consideration these concepts:

  • Network topology

  • Topology changes

  • Trunk failures

  • Trunk repairs

  • Changes in pass sync option on trunks

  • Clock source failures

  • Clock source repairs

Highest clock source refers to a user-configured hierarchy level related to a particular clock source, irrespective of its stratum level. This user-configured hierarchy consists of three levels:

  • Primary

  • Secondary

  • Tertiary

You can configure network clock hierarchy using the cnfclksrc command and display it using the dspclksrcs command. The syntax of these commands varies depending upon platform; details are included in these sections.

Network Clock Sources for Cisco WAN Switches

Independent of the above hierarchy, you can categorize the user-configured clock sources as seen here:

  • Internal Clock Sources

  • External Clock Sources

  • Trunk Clock Sources

  • Circuit Line Clock Sources

Switch software allows you to configure external, trunk, and circuit line types of clock sources at any of the hierarchy levels using the cnfclksrc command. The internal clock source is used as the default clock source in the absence of a user-configured clock source. It is also used when the user-configured clock source is disrupted or unreachable.

Cisco recommends basing the clock source configuration in a given hierarchy level on its stratum level. To verify the hierarchy level of a clock source, issue the dspclksrcs command. Stratum levels are used to describe the accuracy and stability of a clock. This document references stratum levels that range from 1 (most accurate) to 4 (least accurate). A stratum level 4 clock is not as stable as a stratum level 1 clock.

Typically, external clock sources are of the highest stratum level and, at a given hierarchy level, an external clock source would be configured in preference to some other type of clock source. Cisco recommends Y-cabling external clock sources when redundant processors are used.

The internal clock source of the BPX 8600 and MGX 8850 (PXM45) meets stratum Level 3 requirements for accuracy and stability.

These clock source configurations are not supported:

  • A circuit line on the MGX 8220 platform.

  • These port interfaces on BPX, IGX and MGX platforms:

    • V.35

    • X.21

    • RS-232

    • RS-449

    • Frame Relay

Clock Selection in BPX/IPX/IGX Networks

The highest numbered reachable node in a BPX/IPX/IGX network makes the selection of reference clock source for each node in the network. In a 10 node network, node number 10 determines the path to the closest, highest-available stratum clock source for every node in the network. The highest numbered reachable node performs this computation and instructs other nodes to perform any needed switching of clock source references as a result of these network changes:

  • Configuration of a new clock source.

  • Change the pass sync option on a trunk (refer to WAN Switching Network Synchronization Fundamentals).

  • Addition of the addtrk or deltrk commands that change the topology of the network.

  • Trunk failures and repairs.

  • Clock source failures and repairs.

This dynamic clock routing allows a node to make an automated and unattended path switch to the most desirable clock source in the network. In BPX/IPX/IGX networks, dynamic clock routing is controlled by the clock controller, which is a process that runs on the highest numbered reachable node. The clock controller is responsible for distributing new clock paths to all nodes in the network should a clock change occur. These steps illustrate the clock controller actions during one of the network changes listed here.

  1. A network change occurs and is detected by the highest numbered node clock controller as a topology update.

  2. The highest numbered node clock controller calculates new clock paths for affected nodes by building a clock source topology tree and making a shortest hop decision from clock source to network node.

  3. The highest numbered node clock controller sends a network message to all nodes containing the new path they should use.

  4. Each node receives the message and compares the new path with the existing path.

  5. If the paths are different the node acquires the new path just received in the message.

  6. If the paths are the same the node does nothing and dumps the message.

Dynamic clock routing allows for temporarily unavailable clock sources to be automatically reinstated for network-wide synchronization. Whenever the original clock source repairs, the highest numbered reachable node automatically reverts to using it.

The path from a network node to its active clock source only contains trunks that pass clock synchronization. Issue the dsptrkcnf command to verify that the Pass Sync option is set to Yes. If the Pass Sync option is set to Yes then the trunk is configured to pass clock synchronization. To change the Pass Sync option, use the cnftrk command.

If multiple clock sources of same hierarchy level are available, the clock source closest to the node measured in number of hops is chosen for reference. If multiple equidistant equal clock sources are available, the source with or through the lowest logical trunk number, logical line number, or external clock input (EXT1/EXT2) is chosen.

In the absence of any acceptable user, configured clock sources, the internal oscillator of the highest numbered node is used like a user-configured clock source as a reference for all network nodes. If a network node is using the internal oscillator of the highest numbered node as its clock source and the path to the clock is disrupted due to a trunk failure or some other network event, then the node reverts to its own internal oscillator while the new clock path is calculated by the highest numbered node. The highest numbered node calculates the clock path for the network node and instructs the network node of the new path to use. The highest numbered node is responsible for node synchronization via timing conveyed on the network trunks or lines as displayed using the dspcurclk command. In large networks, the calculations performed by the highest numbered node place additional burden on the active processor card. Avoid configuring the highest numbered node as a Cisco WAN Manager (CWM) gateway; refer to Chapter 12: Networking of Cisco WAN Manager Operations. Switch software release 8.4 and later is optimized to reduce the burden on the active processor card of the highest numbered node by only requiring clock routing to be performed for network nodes that do not have a configured and usable external clock source.

Software selects these preferred clock sources for network-wide synchronization:

  • User configured clock sources.

  • The internal oscillator of the highest numbered BPX.

The BPX does not use the following clock sources.

  • The internal oscillator of an IGX or IPX.

  • User-configured clock from an IPX/IGX reference.

  • User-configured clock that has a path through an IPX/IGX node.

In a mixed network with BPX and IGX switches, all IGX switches can use the user-configured clock source of an IGX circuit line, while all BPX switches use the internal oscillator of the highest numbered reachable BPX. For additional information about BPX/IPX/IGX network synchronization, refer to of .

The revertive behavior of BPX/IGX clocking is provided in the table below. For revertive clocking, if the BPX/IGX is configured to use a clock input as its clock source and that clock source fails, the BPX/IGX abandons the clock source and finds an alternate clock source. When the clock source repairs, the BPX/IGX automatically reverts to using it. Non-revertive behavior requires manual intervention to restore the BPX/IGX to the original clock source. An example of manual intervention is having to issue the clrclkalm command to restore a clock source.

Clock Source Reason for Failure BPX* IGX
Trunk or Circuit Line Physical failure such as loss of signal (LOS) Revertive Revertive
  Clock source or clock path is out of specification Non-revertive Non-revertive
External Clock Input Physical failure such as LOS Revertive Non-revertive
  Clock source is out of specification Revertive Non-revertive

* This behavior applies to the BPX BCC-3 or BCC-4 using switch software release 8.4 and higher.

Clock Selection in MGX Networks

MGX 8220 and MGX 8250/8850 (PXM1) nodes do not pass synchronization information across their trunks or lines. Each MGX 8220 and MGX 8250/8850 (PXM1) node terminates clock.

The MGX 8220 user-configured clock sources can be categorized into the following:

  • Internal Clock Source

  • External T1 or E1 Clock Source

  • Trunk Clock Source from BPX

The MGX 8250/8850 (PXM1) user-configured clock sources can be categorized into the following:

  • Internal Clock Source

  • External T1 or E1 Clock Source

  • Trunk Clock Source from BPX

  • Circuit Line Clock Source

In the absence of any acceptable user-configured clock sources, the internal oscillator of the MGX 8220 and MGX 8250/8850 (PXM1) is used.

MGX 8850 (PXM45) switches pass synchronization information across AXSM trunks. All network clock sources must be user-configured as software does not delegate clock synchronization to one node as in BPX/IPX/IGX switch networks. The MGX 8850 (PXM45) has stratum level 3 clock circuitry on the PXM-UI-S3 backcard and in the absence of any acceptable user-configured clock sources, this clock is used. This internal oscillator provides the default synchronization signal for the switch. Alternatively, you can configure the following external clock sources:

  • T1, E1, or Building Integrated Timing Supply (BITS) clock source on the PXM45 back card.

  • A port on an AXSM.

The MGX8850 (PXM1 and PXM45) external clock source can be configured to be revertive, whereas PXM line or AUSM/CESM line clock sources are non-revertive. For revertive clocking, if the MGX 8800 is configured to use the external clock input as its clock source and the external clock source fails due to a physical failure, such as LOS or the clock frequency drifting out of tolerance, the MGX 8800 abandons the clock source and finds an alternate clock source. Whenever the external clock source repairs, the MGX 8800 automatically reverts to using it.

The following diagram shows the possible clock sources for the MGX 8850 (PXM45).

mgx8850_clock.gif

Configuring IGX Clock Sources

In this example, the T1 line between a private branch exchange (PBX) and an IGX 8400 Series Switch is configured as the primary network clock source. The steps required to manually configure the target IGX, IGX2, to have the highest node number are also provided. As the highest numbered network node, in event of the PBX T1 line failure, the internal oscillator of IGX2 takes over as the network clock source until the T1 line is active again.

This configuration example does not provide design guidance for network synchronization, it is only an aid to configure clocking on Cisco IGX 8400 Series Switches.

Network Diagram

igx8400_clock.gif

Configuration Tasks Performed

It is assumed that all trunks and lines are enabled and added. The detailed steps below lead you through the following configuration tasks:

  • Configure the T3 trunk between IGX1 and IGX2 to pass clock synchronization information.

  • Confirm that PBX2 is providing a clock on the T1 line between PBX2 and IGX2.

  • Configure the T1 line between PBX2 and IGX2 as the network clock source.

Step-by-step

Complete these steps.

  1. Log on to IGX2 as SuperUser using the Telnet or the maintenance port.

  2. Verify that the trunk can pass clock synchronization information between IGX2 and IGX1 using the dsptrkcnf command.

    IGX2       TRM   SuperUser       IGX 8420  9.2.34    July 28 2001 07:29 GMT 
    
    
    TRK 10.1 Config       T3/636   [96000 cps]  UXM slot:10                        
    Transmit Trunk Rate:  96000  cps          Payload Scramble:     No           
    Rcv Trunk Rate:       96000  cps          Connection Channels:  256          
    Pass sync:            Yes                 Gateway Channels:     200          
    Loop clock:           No                  Traffic:V,TS,NTS,FR,FST,CBR,N&RVBR,ABR
    Statistical Reserve:  1000   cps          Deroute delay time:   0 seconds    
    Header Type:          NNI                 VC Shaping:           No           
    VPI Address:          1                   VPC Conns disabled:   No           
    Routing Cost:         10                 
    Idle code:            7F hex             
    Restrict PCC traffic: No                 
    Link type:            Terrestrial        
    Line framing:         PLCP               
    Line cable length:    0-225 ft.          
    HCS Masking:          Yes                
                                                                                    
    Last Command: dsptrkcnf 10.1
    

    Verify the parameters Line framing and Pass sync. If Pass sync is No, configure the trunk to pass clock synchronization information by setting Pass sync to Yes using the cnftrk command. The options for Line framing on an IGX 8400 UXM ATM T3 (DS3) trunk are header error checksum (HEC) and payload convergence protocol (PLCP). In this example, PLCP line framing is used.

  3. Issue the drtop command from either IGX 8400 switch to verify the node numbers. Use the command output below to verify that IGX1 has a higher network node number than IGX2.

    IGX2             TN    SuperUser       IGX 8420  9.2.34    July 29 2001 07:13 GMT 
    
    
    Node #   Node Name     Hops To  Via Trk  SAT Hops  No HP Hops  Open Space
    31       D1.IGX2         0     0        0         0          0           0
    32       D1.IGX1         1     0        6         0          0           3
    
                                                                                    
    Last Command: drtop
    

    Configure IGX2 to have the highest network node number. This configuration specifies that the internal oscillator of IGX2 becomes the network clock source should the primary configured clock source fail. To understand the significance of node numbering refer to the Understanding Clock Selection in BPX/IPX/IGX Networks section. Changing the node number on a BPX/IPX/IGX switch is accomplished using the Service-level rnmnd command. This command has significant impact in large networks and must be used with caution.

    IGX2   TN    Service  IGX 8420  9.2.34    July 29 2001 07:24 GMT 
    
    NodeName J/Num
    IGX1        /32
    IGX2        /33
                                                                                    
    Last Command: rnmnd 33
    
  4. Issue the vt IGX1 command and then verify the current clock source using the dspcurclk command.

    IGX1   VT    SuperUser  IGX 8420  9.2.34    July 29 2001 07:37 GMT 
    
                                 Current Clock Source
    
    Source Node:     IGX2
    Source Line:     Internal
    Clock Type:                 
    Clock Frequency: 1544011
    Path to Source:
       IGX1       10.1-- 10.1IGX2      
                                                                                 
    Last Command: dspcurclk
    
  5. Issue the bye command to return to IGX2 and then verify the current clock source using the dspcurclk command.

    IGX2     TN    SuperUser  IGX 8420  9.2.34    July 29 2001 07:38 GMT 
    
                                 Current Clock Source
    
    Source Node:     IGX2
    Source Line:     Internal (SCC)
    Clock Type:                 
    Clock Frequency: 1543943
    
    Node is currently receiving clock from its internal oscillator.
                                                                                    
    Last Command: dspcurclk
    
  6. Confirm that PBX2 is providing a clock on the T1 line between PBX2 and IGX2. The command to verify clock on PBX2 varies based on the make and model of PBX. It is required to verify PBX2 configuration prior to configuring the T1 line as a primary network clock source.

  7. Configure the T1 line to the PBX on IGX2 as the primary network clock source using the cnfclksrc command. The T1 line must be up and free of alarm to be configured as a network clock source.

    IGX2     TN    SuperUser  IGX 8420  9.2.34    July 29 2001 07:40 GMT 
    
                                Network Clock Sources
    
    Primary
    IGX2       LINE   7.1
    
    Secondary
    None
    
    Tertiary
    None
    
                                                                       
    Last Command: cnfclksrc c 7.1 p
    
      
    
    Syntax: cnfclksrc <line type> <line number> <source type> [freq]
    where : 
    
            <line type> - Circuit(c), Packet(p) or External(e)
            <line number> - Circuit line number, Packet(trunk) number or External clock source number
            <source type> - Primary(p), Secondary(s) or Tertiary(t)
            [freq] - (optional parameter for line type 'c' and 'p') 
                      Specifies the frequency of the clock source. 
                      An entry is necessary only if the line type is an external line. 
                      The supported frequencies are 1.544 MHz and 2.048 MHz. 
                      Enter a "1" for 1.544 MHz or a "2" for 2.048 MHz. 
  8. Verify the current clock source on IGX1 and IGX2 using the dspcurclk command.

    IGX2             TN    SuperUser         IGX 8420  9.2.34    July 29 2001 07:48 GMT 
    
                                 Current Clock Source
    
    Source Node:     IGX2
    Source Line:     LINE  7.1
    Clock Type:      Primary   
    Clock Frequency: 1543945
                                                                        
    Last Command: dspcurclk
    
     
    
    IGX1             VT    SuperUser         IGX 8420  9.2.34    July 29 2001 07:50 GMT
    
                                 Current Clock Source
    
    Source Node:     IGX2
    Source Line:     LINE  7.1
    Clock Type:      Primary   
    Clock Frequency: 1544012
    Path to Source:
       IGX1       10.1-- 10.1IGX2      
                                                                                  
    Last Command: dspcurclk
    
  9. To minimize clocking discrepancies in the network, the PBX connected to IGX1 should be configured to derive clock synchronization from the T1 line. If the PBX can't be configured to use the clock coming from the IGX1 T1 line, configure the T1 line on the IGX1 to loop the clock using the cnfln command. Toggle the parameter Loop Clock to Yes if it is set to No.

Note: Frame slips may be recorded on the IGX1 line if either of the following is true:

  • The line clock is looped as mentioned above.

  • The line clock is not looped and the PBX is not configured to take clock from the IGX1 T1 line.

To view frame slips, use the dsplnerrs <line#> command. For more information related to clocking errors, refer to WAN Switching Network Synchronization Fundamentals.

For more information on clock synchronization and clock synchronization commands, refer to Synchronizing Network Clocks.

Configuring BPX, MGX 8220, MGX 8250/8850 (PXM 1) Clock Sources

In this example, the internal oscillator of a Cisco BPX 8600 Series switch is the primary network clock source. If the switch fails or if any of the devices can not find a path to the BPX, the device runs the Automatic Node Clock Selection Algorithm to choose the next best available clock source. The MGX 8220 and MGX 8850 (PXM1) devices are connected as feeder shelves to BPX1 and BPX2, respectively. MGX1 can be configured to accept primary and secondary clock sources. The clock configuration on MGX1 and MGX2 feeder shelves is limited to the local shelf and is not propagated to other nodes in the network.

This configuration example does not provide design guidance for network synchronization, it is only an aid to configure clocking on Cisco WAN switches.

bpx_mgx_clock.gif

Tasks Performed

It is assumed that all trunks and lines are enabled and added.

  1. Configure all trunks on BPX1 to pass clocking information.

  2. Configure one of the T3 trunks between BPX2 and IGX1 to pass clocking information.

  3. Verify that the internal oscillator of BPX1 is the primary network clock source.

  4. Configure MGX1 and MGX2 to derive clock synchronization from their respective feeder trunks.

Step-by-Step

Complete these steps.

  1. Log on to BPX1, BPX2 and IGX1 as SuperUser using the Telnet or maintenance port.

  2. Verify that all the trunks on BPX1 can pass clock synchronization information using the dsptrkcnf command. Examine the parameter Pass sync on all trunks. If Pass sync is No, configure the trunk to pass clock synchronization information by setting Pass sync to Yes using the cnftrk command. The options for Line framing on an IGX 8400 UXM ATM T3 (DS3) trunk are header error checksum (HEC) and payload convergence protocol (PLCP). In this example, PLCP line framing is used.

  3. Verify that the T3 trunk between BPX2 and IGX1 can pass clock synchronization information using the dsptrkcnf command. Ensure that the parameter Pass sync is set to Yes.

  4. Verify the node numbers on the BPX and IGX switches using the drtop command.

    BPX1             TRM   SuperUser         BPX 8620  9.2.34    July 29 2001 12:34 GMT 
    
    Node #   Node Name     Hops  IPX Hops  Via Trk  SAT Hops  No HP Hops  Open Space
    33       D1.IGX1         2     0          3.2      0         0           3
    53       D1.BPX2         1     0          3.2      0         0           96
    59       D1.BPX1         0     0            0      0         0           0
                                                                          
    Last Command: drtop
    

    Since there are no clock sources defined by user configuration in the network, the internal oscillator of BPX1 becomes the primary network clock source. To understand the significance of node numbering refer to the Understanding Clock Selection in BPX/IPX/IGX Networks section.

  5. Verify the current clock source on BPX1, BPX2 and IGX1 using the dspcurclk command.

    BPX1  TRM   SuperUser BPX 8620  9.2.34    July 30 2001 01:54 GMT 
    
                                 Current Clock Source
    
    Source Node:     BPX1
    Source Line:     Internal (CC)
    
    Clock Type:                 
    Clock Frequency: 1544000
    
    Node is currently receiving clock from its internal oscillator.
                                                                         
    Last Command: dspcurclk
    
  6. Issue the VT BPX2 command and then verify the current clock source using the dspcurclk command.

    BPX2             VT    SuperUser         BPX 8620  9.2.34    July 30 2001 01:55 GMT 
    
                                 Current Clock Source
    
    Source Node:     BPX1
    Source Line:     Internal (CC)
    
    Clock Type:                 
    Clock Frequency: 1544000
    Path to Source:
       BPX2      11.2--BPX1
                                                                                    
    Last Command: dspcurclk
    
  7. Issue the bye command to return to BPX1. Issue the VT IGX1 command and then verify the current clock source using the dspcurclk command.

    IGX1   TRM   SuperUser  IGX 8420  9.2.34    July 30 2001 02:13 GMT 
    
                                 Current Clock Source
    
    Source Node:     BPX1
    Source Line:     Internal
    Clock Type:                 
    Clock Frequency: 1543977
    Path to Source:
       IGX1       6-- 4.3BPX2      11.2-- 3.2BPX1 
    
    Last Command: dspcurclk
    
  8. Configure MGX2 to take timing from its feeder trunk.

    mgx2.1.7.PXM.a > dspclksrc
        Table empty: mibparDspClkSrc
    
    mgx2.1.7.PXM.a > cnfclksrc 7.1 P
    Trunk passing Sync cannot be clock source
    Set failed due to illegal option value(s)
    
            <slot.port> -- (?)
            <clktyp> Primary(P)/Secondary(S)/Tertiary(T)/Null(N) -- (?)
    
    Syntax: cnftrk "-slot.port ... -stres <Stats Reserve> -ccrstr <CC Restrict> -lntyp <Line Type> 
    -passsync <yes/no> -drtdly <Deroute Delay(ms)> -fst <yes/no> -fr <yes/no> -nts <yes/no> -ts 
    <yes/no> -voice <yes/no> -cbr <yes/no> -vbr <yes/no> -abr <yes/no> -rtcost <RoutingCost>
    -vpcconid <Max VpcConids>" to configure various trunk parameters
        -slot.port ...
        -stres <Stats Reserve>
        -ccrstr <CC Restrict>
        -lntyp <Line Type>
        -passsync <yes/no>
        -drtdly <Deroute Delay(ms)>
        -fst <yes/no>
        Fr <yes/no>
        -nts <yes/no>
        Ts <yes/no>
        -voice <yes/no>
        -cbr <yes/no>
        -vbr <yes/no>
        -abr <yes/no>
        -rtcost <RoutingCost>
        -vpcconid <Max VpcConids>
    
    mgx2.1.7.PXM.a > cnftrk -slot.port 7.1 -passsync no
    mgx2.1.7.PXM.a > cnfclksrc 7.1 P
    mgx2.1.7.PXM.a > dspclksrc
    Interface    Clock Type     Clock Source
    ---------    ----------     ------------
      7.1          PRI           INTERFACE 
    
    mgx2.1.7.PXM.a > dspcurclk
            Current Clock Source 
          ----------------------
    Source Node: mgx2
    Source Line: 7.1
    Clock Level: PRI
    Clock Type : TRK INTERFACE
  9. Configure MGX1 to accept the timing from the BPX feeder trunk as a primary clock and to use its internal oscillator as the secondary clock. For this example, both the primary and secondary clock sources must be reconfigured and MGX1 must be directed to use the primary clock source as its current clock.

    mgx1.1.4.ASC.a > dspclksrc
    
      PrimaryClockSource:   External T1/E1 from C.O.
      SecondaryClockSource: Inband from BNM
      CurrentClockSource:   Secondary
      ClockSwitchState:     SrcChanged
      ExtClkPresent:        Not Present
      ExtClkSrcImpedance:   100 ohms
      ExtClkConnectorType:  DB-15
    
    mgx1.1.4.ASC.a > cnfclksrc
    
    cnfclksrc "-pri <PrimaryClkSrc> -sec <SecondaryClkSrc>  -cur <CurrentClkSrc>
    -imp <ExternalClkSrcImpedance>"
      -pri  where PrimaryClockSource = 1 - 3
         1: Internal 2: BNM Inband 3: External
      -sec  where SecondaryClockSource = 1 - 3
         1: Internal 2: BNM Inband 3: External
      -cur  where CurrentClockSource = 1 - 3,
         1: Primary  2: Secondary  3: Internal
      -imp  where ExternalClkSrcImpedance = 1(BNM-155 only,
        1: 75 ohms 2: 100 ohms   3: 120 ohms
    
    mgx1.1.4.ASC.a > cnfclksrc -pri 2
    
    mgx1.1.4.ASC.a > dspclksrc
    
    
      PrimaryClockSource:   Inband from BNM
      SecondaryClockSource: Inband from BNM
      CurrentClockSource:   Secondary
      ClockSwitchState:     NoChange
      ExtClkPresent:        Not Present
      ExtClkSrcImpedance:   100 ohms
      ExtClkConnectorType:  DB-15
    
    mgx1.1.4.ASC.a > cnfclksrc -cur 1
    
      PrimaryClockSource:   Inband from BNM
      SecondaryClockSource: Inband from BNM
      CurrentClockSource:   Primary
      ClockSwitchState:     NoChange
      ExtClkPresent:        Not Present
      ExtClkSrcImpedance:   100 ohms
      ExtClkConnectorType:  DB-15
    
    mgx1.1.4.ASC.a > cnfclksrc -sec 1
    
    mgx1.1.4.ASC.a > dspclksrc
    
      PrimaryClockSource:   Inband from BNM
      SecondaryClockSource: Internal Oscillator
      CurrentClockSource:   Primary
      ClockSwitchState:     NoChange
      ExtClkPresent:        Not Present
      ExtClkSrcImpedance:   100 ohms
      ExtClkConnectorType:  DB-15

Configuring MGX 8850 (PXM45) Clock Sources

This example shows an MGX 8850 network with three switches, one of which has been configured as the master clock source for the network. The remaining switches in the network receive their primary clock from an incoming AXSM line. Switch 2 receives the clock directly from Switch 1 and Switch 3 synchronizes to the master clock that is relayed by Switch 2.

This configuration example does not provide design guidance for network synchronization, it is only an aid to configure clocking on Cisco MGX 8850 Series switches.

axsm_clock.gif

Tasks Performed

It is assumed that all resource partitions, trunks, lines and ports are enabled and appropriately configured.

  1. Configure Switch1 as the master clock source.

  2. Configure Switches 2 and 3 to receive the clock source on the AXSM line.

Step-by-Step

Complete these steps.

  1. Log on to the switches with GROUP1 privileges using the Telnet or the maintenance port.

  2. Verify the current clock source on Switch1 using the dspclksrcs command.

    This command output shows a display with neither primary nor secondary clocks configured. This is the default configuration of a switch, which uses the internal clock as the clock source. Whenever the active clock is listed as null, the switch is using the internal clock.

    switch1.7.PXM.a > dspclksrcs
    
    Primary clock type:     null     
    Primary clock source:   0.0            
    Primary clock status:   not configured 
    Primary clock reason:   okay                                          
    Secondary clock type:   null     
    Secondary clock source: 0.0            
    Secondary clock status: not configured 
    Secondary clock reason: okay                                          
    Active clock:           internal clock 
    source switchover mode: non-revertive  
    
    switch1.7.PXM.a > 
  3. Configure Switch2 to receive its clock source from Switch1 via the AXSM line between them. Check the status of the AXSM line and port before configuring it is as the clock source.

    switch2.7.PXM.a > cc 9
    
    (session redirected)
    
    switch2.9.AXSM.a > dspln -ds3 2.8
      
      Line Number         : 2.8
      Admin Status        : Up                Alarm Status        : Clear
      Line Type           : ds3cbitplcp       Number of ports     : 1
      Line Coding         : ds3B3ZS           Number of partitions: 1
      Line Length(meters) : 0                 Number of SPVC      : 0
      OOFCriteria         : 3Of8Bits          Number of SPVP      : 0
      AIS c-Bits Check    : Check             Number of SVC       : 3
      Loopback            : NoLoop
      Xmt. Clock source   : localTiming
      Rcv FEAC Validation : 4 out of 5 FEAC codes
    
    switch2.9.AXSM.a > dspports
    
    ifNum Line Admin Oper. Guaranteed Maximum     Port SCT Id     ifType  VPI
               State State Rate       Rate                               (VNNI only)
    ----- ---- ----- ----- ---------- --------- ----------------- ------ ----------
       11  1.1    Up    Up      96000     96000   2                   UNI    0 
       28  2.8    Up    Up      96000     96000 106                   NNI    0 
    switch2.9.AXSM.a > dspport 28
    
      Interface Number               : 28
      Line Number                    : 2.8
      Admin State                    : Up        Operational State   : Up
      Guaranteed bandwidth(cells/sec): 96000     Number of partitions: 1
      Maximum bandwidth(cells/sec)   : 96000     Number of SPVC      : 0
      ifType                         : NNI       Number of SPVP      : 0
      Port SCT Id                    : 106 
      VPI number(VNNI only)         : 0         Number of SVC       : 3
  4. After ensuring that the line and the logical port are operational and clear of alarms, configure the line as the clock source on the Active PXM using the cnfclksrc command.

    switch2.9.AXSM.a > cc 7
    
    (session redirected)
    
    switch2.7.PXM.a > dspclksrcs
    
    Primary clock type:     null     
    Primary clock source:   0.0            
    Primary clock status:   not configured 
    Primary clock reason:   okay                                          
    Secondary clock type:   null     
    Secondary clock source: 0.0            
    Secondary clock status: not configured 
    Secondary clock reason: okay                                          
    Active clock:           internal clock 
    source switchover mode: non-revertive  
    
    switch2.7.PXM.a > cnfclksrc
    
    Syntax: cnfclksrc   
    
           [ -bits { e1|t1 } ]
    
           [ -revertive { enable|disable } ]
    
            priority -- primary|secondary (default=primary)
            shelf.slot:subslot.port:subport -- [shelf.]slot[:subslot].port[:subport0
            bits -- bits {e1|t1 (default=null)}
            revertive -- revertive{enable|disable (default=disable)}
    
            possible errors are:
    
    
    switch2.7.PXM.a > cnfclksrc primary 9:2.8:28
    Clock Manager has been sucessfully updated.
    
    switch2.7.PXM.a > dspclksrcs
    
    Primary clock type:     generic  
    Primary clock source:   9:2.8:28       
    Primary clock status:   ok       
    Primary clock reason:   locked                                        
    Secondary clock type:   null     
    Secondary clock source: 0.0            
    Secondary clock status: not configured 
    Secondary clock reason: okay                                          
    Active clock:           primary    
    source switchover mode: non-revertive  
    
    switch2.7.PXM.a > 
  5. Configure Switch3 to receive the clock source from Switch1 via the AXSM line between Switch2 and Switch3. Check the status of the AXSM line and port before configuring it is as the clock source.

    switch3.7.PXM.a > cc 1
    
    (session redirected)
    
    switch3.1.AXSM.a > dspln -sonet 2.8
      
      Line Number            : 2.8
      Admin Status           : Up                Alarm Status        : Clear
      Loopback               : NoLoop            APS enabled         : Disable
      Frame Scrambling       : Enable            Number of ports     : 1
      Xmt Clock source       : localTiming       Number of partitions: 1
      Line Type              : sonetSts3c        Number of SPVC      : 0
      Medium Type(SONET/SDH) : SONET             Number of SPVP      : 0
      Medium Time Elapsed    : 498381            Number of SVC       : 2
      Medium Valid Intervals : 96
      Medium Line Type       : MMF
    
    switch3.1.AXSM.a > dspports
    
    ifNum Line Admin Oper. Guaranteed Maximum     Port SCT Id     ifType  VPI
               State State Rate       Rate                               (VNNI only)
    ----- ---- ----- ----- ---------- --------- ----------------- ------ ----------
       27  2.7    Up  Down     353207    353207   3                   NNI    0 
       28  2.8    Up    Up     353207    353207   3                   NNI    0 
    
    switch3.1.AXSM.a > dspport 28
    
      Interface Number               : 28
      Line Number                    : 2.8
      Admin State                    : Up        Operational State   : Up
      Guaranteed bandwidth(cells/sec): 353207    Number of partitions: 1
      Maximum bandwidth(cells/sec)   : 353207    Number of SPVC      : 0
      ifType                         : NNI       Number of SPVP      : 0
      Port SCT Id                    : 3 
      VPI number(VNNI only)          : 0         Number of SVC       : 2
    
    switch3.1.AXSM.a > 
  6. Now configure the line as the clock source on the active PXM.

    switch3.1.AXSM.a > cc 7
    
    (session redirected)
    
    switch3.7.PXM.a > cnfclksrc primary 1:2.8:28                  
    Clock Manager has been sucessfully updated.
    
    switch3.7.PXM.a > dspclksrcs
    
    Primary clock type:     generic  
    Primary clock source:   1:2.8:28       
    Primary clock status:   OK       
    Primary clock reason:   locked                    
    Secondary clock type:   null     
    Secondary clock source: 0.0            
    Secondary clock status: not configured 
    Secondary clock reason: okay                                          
    Active clock:           primary    
    source switchover mode: non-revertive  
    
    switch3.7.PXM.a > 

    For more information on clocking configuration and related commands for the MGX 8850 (PXM45) refer to Shelf Management Commands, and the section Managing Network Clock Sources in Switch Operating Procedures.

Clock Configuration and Verification Commands

BPX/IGX/IPX

  • cnfclksrc—This command configures a primary, secondary, or tertiary clock network-wide clock source. Issue this command to add, delete or change a clock source. If a trunk is specified as a clock source, then the trunk must be configured to not pass clock using the cnftrk command and setting the Pass sync option to No.

    The BPX external clock input requires either:

    • a T1 alternate mark inversion (AMI) bipolar frequency signal for the DB15 connector;

    • an E1 high density bipolar 3-zero (HDB3) signal for the BNC connector.

      The IGX external clock input requires a 1544 kHz or 2048 kHz RS-422 square wave, which is an all pulses positive or unipolar signal for the DB15 connector. This means a standard T1 or E1 input is not acceptable as an external clock input for the IGX. A stratum clock source such as a Hewlett-Packard GPS receiver that provides either a 1544 kHz or 2048 kHz unipolar square wave reference frequency is acceptable as an external clock input for the IGX.

  • dspclksrcs—This command displays all configured clock sources in the network.

  • dspcurclk—This command displays the current reference clock source for the node on which it is issued and the path to that clock source.

  • dspstbyclk—This BPX only command displays the external clock input on the standby BCC backcard. The command output may have anomalous results if both BCC backcards are not Y-cabled to the same external clock input.

  • dspsecclkcnf—This BPX only command displays the secondary external clock input line. It compares the input line to the reference clock on the active BCC backcard. This command allows you to validate the secondary external clock input when two external clock inputs are configured.

MGX 8220

  • cnfclksrc—This command configures the primary, secondary, or internal clock source for the shelf. The cnfclksrc command must be issued from the active ASC. Any combination of clocks are configurable and in any order. This command can also be used on the IMATM service module (SM) to configure primary, secondary, or current clock source. For IMATM configuration, the following clock sources can be used:

    • DS1 or E1 lines

    • DS3 or E3 lines

    • internal clock

  • cnfsrmclksrc—Issue this command on the active ASC to configure clock source for the SRM. The clock source can be from either the BNM or the SRM T3 line.

  • dspclksrc—Issue this command on the active ASC to display all the clock sources for the shelf. This command can also be used on the IMATM service module to display all the clock sources for the SM.

  • dspsrmclksrc—Issue this command on the active ASC to display the SRM clock sources for all the T3 or E3 lines.

MGX 8250, MGX 8850 (PXM1)

The MGX 8250 and MGX 8850 (PXM1) allow a table of multiple primary, secondary and tertiary clock sources, however the default clock source is set to the internal oscillator. Commands to configure clock source are:

  • cnfclksrc—This command configures the primary, secondary, or internal clock source for the shelf. The cnfclksrc command must be issued from the active PXM. It is recommended to configure one clock source at a time. Any combination of clocks are configurable and in any order. This command can also be used on the IMATM service module to configure primary, secondary, or current clock source. For IMATM configuration, the following clock sources can be used

    • DS1 or E1 lines

    • DS3 or E3 lines

    • internal clock

    Before using the cnfclksrc command, the PXM1 broadband interfaces and lines must be configured. First issue the addln command, then the addport command.

  • cnfextclk—Issue this command on the active PXM to configure the external clock source line and impedance. The command allows you to specify the ohm level on the E1 or T1 interface.

  • cnfclklevel—Issue this command on the active PXM running 1.1.31 or higher to configure the stratum level of the clock source.

  • cnfsrmclksrc—Issue this command on the active PXM to configure clock source for the SRM. The clock source can be from either the internal clock source or the SRM T3 line.

  • dspclkinfo—Issue this command on the PXM to display detailed information about all the configured clock sources in the node.

  • dspclksrc—Issue this command on the PXM to display the configured clock sources on the shelf. This command can also be used on the IMATM service module to display all the clock sources for the service module.

  • dspcurclk—Issue this command on the PXM to display the current clock source for the shelf.

  • dspsrmclksrc—Issue this command on the PXM to display the SRM clock sources for the T3 lines.

MGX 8850 (PXM45)

  • cnfclksrc - Issue this command on the active PXM to configure primary, secondary, or BITS clocks, or the revertive option for the BITS clock.

  • cnfclkparms - Issue this command on the active PXM to configure the signal type and the cable type for an E1 BITS clock. The default values are 2 - signal type is sync and 1 - cable type is twisted pair. If either the signal type is data or the cable type is coaxial, then the incoming clock signal will not be terminated properly and the software will fail to detect activity on the external clock port. The cnfclkparms command is used to input the correct signal and cable type to the system.

    The signal type can be sync or data. Sync and data are two different signal formats that indicate how the line interface unit (LIU) should extract clock from the input. Data signal type requires the LIU to understand the Tip (hot) and Ring (return) positions for the input signal and extract synchronizing information from that input. Sync signal type is an independent clock signal where the LIU does not have to extract synchronizing information from the input pulse.

  • dspclksrcs - Issue this command on the PXM to display the configuration and status of the clock sources.

  • delclksrc -Issue this SuperUser command on the active PXM to delete or change the priority of a user-specified primary or secondary clock source.

Troubleshoot

BPX/IGX/IPX

  • clkdb - A Service level command that displays information on the clock as distributed in the synchronization messages. The clkdb command is used to view the current entry in the clock database. To obtain a recent view of the clock database issue the clkdb clear command and then reissue the clkdb command. The clock database is a circular memory area that is 10 entries long.

    Periodically, the node executes an algorithm in which the frequency of the network clock is measured and compared to the node's internal oscillator. The internal oscillator is a crystal that vibrates at the frequency of 8.192 MHz for the IPX, IGX and BPX. This frequency is compared to what is received from the line, trunk or external clock source, which are all 8 kHz references. If the comparison is off by more than a specified amount, a clock fault is recorded. The node then tries to identify where the clock fault lies.

    The fault isolation routine samples the system clock signal and stores the information in one of the database entries. In the screen display below, the clock looks good. There are no failures in the slot or line and there are no bad samples. The Bad Ref: field has a dash, meaning the clock reference is not bad. Two other fields that are important are:

    • last 10 sec. freq.s which indicates the difference between the internal and reference clock sources. In the following display there is no difference which is good.

    • Trail which displays the last 30 events that were logged when the node identified a fault and attempted to correct it. In the following display the event 14 is logged which indicates a clear path clock alarm.

      b1             TN    Service         BPX 8620  9.2.33    Aug. 15 2001 14:47 GMT 
      
      
      CLOCK INFO
      Average Clock:       1544000           Receiver:      Clock Fault Isolation
      Cur index:           1                 Failing Slot:  No current failure
      Total Good:          2706571           Failing Line:  No current failure
      Total Bad:           0                 Errors:        0 out of 10
      Total Samples:       2706571           Last Pass:     No Failure
      Zero DAC count:      0                 BusSigCnt,Alm:  0, -
      Bad Ref: -                             BusSigCnt Tot: 0
      Max, Min DAC:        0, 0              Sec Trial,Good:0, 0
      last 10 frequencies:        0,        0,        0,        0,        0, 
                                  0,        0,        0,        0,        0, 
      last 10 sec. freq.s:        0,        0,        0,        0,        0, 
                                  0,        0,        0,        0,        0, 
      Trail: 14, 14,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 
              0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0, 
                                                                                      
      Last Command: clkdb
      
  • clrclkalm - This command clears a Bad clock source or Bad clock path alarm. The Bad clock source and Bad clock path alarms latch and before the node can use the original clock source, the clrclkalm command must be issued.

  • cnfln - This command configures a line and can be used to toggle the Loop Clock setting between an IGX and a PBX. Toggling Loop Clock may temporarily stop Frame Slips on a line and clear PBX errors, but this is not a substitute for correcting the line's clocking architecture to eliminate all Frame Slips.

  • dclk - A Service level command that displays a running sample of the source clock frequency and the system clock frequency. It is extremely helpful in watching short-term deviations in the frequency.

    b1  TRM   Service     BPX 8620  9.2.34    Aug. 1 2001  03:42 GMT 
    
    Sample T-1     UP frq. DAC     Dev ppm  Sample T-1     UP frq. DAC     Dev PPM
    1 -    1544000 0       -1134   0.00
    2 -    1544000 0       -1134   0.00
    3 -    1544000 0       -1134   0.00
    4 -    1544000 0       -1134   0.00
    5 -    1544000 0       -1134   0.00
    6 -    1544000 0       -1134   0.00
    7 -    1544000 0       -1134   0.00
    8 -    1544000 0       -1134   0.00
    9 -    1544000 0       -1134   0.00
    10 -   1544000 0       -1134   0.00
    11 -   1544000 0       -1134   0.00
    12 -   1544000 0       -1134   0.00
                                                                        
    This Command: dclk
    
    Hit DEL key to quit

    In the command output above:

    • DAC is the value input to the digital-to-analog converter (DAC) to provide the correcting voltage to the phase locked loop (PLL) oscillator.

    • UP frq. is the BPX Utility Processor (UP) frequency change required to bring the oscillator to the correct frequency.

Output of the dclk command provides a useful measure of the stability of clock samples. If only one sample is displayed, or the samples vary wildly, a switchcc may be required. Additional troubleshooting and problem isolation is required prior to issuing the switchcc command due to the potential negative impact to the network switch.

It is normal for the dclk command output at each node to be completely different. The dclk command displays the measurement of the local node frequency as measured by an oscillator on the active processor. Since each node uses a different local processor oscillator, the dclk command output displays different measurements of the same frequency.

MGX 8220

dspclksrc - A command that displays information about the current and configured clock sources. It has been noted that the BNM-155 may exhibit non-revertive behavior. If the BNM-155 is configured as the primary clock source and experiences a failure that is subsequently corrected, manual intervention may be required to restore the MGX 8220 CurrentClockSource to Inband from BNM. Issue the cnfclksrc command and reconfigure the BNM-155 as the primary clock source.

Related Information

Updated: Apr 17, 2009
Document ID: 4400