The Cisco® I-Flex design combines shared port adapters (SPAs) and SPA interface processors (SIPs), using an extensible design that enables service prioritization for voice, video, and data services. Enterprise and service provider customers can use the improved slot economics resulting from modular port adapters that are interchangeable across Cisco routing platforms. The I-Flex design maximizes connectivity options and offers superior service intelligence through programmable interface processors, which deliver line-rate performance. I-Flex enhances speed-to-service revenue and provides a rich set of quality-of-service (QoS) features for premium service delivery while effectively reducing the overall cost of ownership. This data sheet contains the specifications for the Cisco 24-port Channelized T1/E1/J1 circuit emulation over packet and ATM SPA (refer to Figure 1).
Figure 1. 24-Port Channelized T1/E1/J1 Circuit Emulation Network and ATM Shared Port Adapter
The Cisco 24-port Channelized T1/E1/J1 circuit emulation over packet and ATM SPAs are available on high-end Cisco routing platforms offering the benefits of network scalability with lower initial costs and ease of upgrades. The Cisco SPA/SIP portfolio continues the Cisco focus on investment protection along with consistent feature support, broad interface availability, and the latest technology. The Cisco SPA/SIP portfolio allows different interfaces (Packet over SONET/SDH [POS], ATM, Ethernet, and so on) to be deployed on the same interface processor.
The Circuit Emulation over Packet (CEoP) SPAs provide a new service offering. These SPAs provide bit-transparent data transport that is completely protocol independent. For the first time, this allows network administrators to use their existing IP/Multiprotocol Label Switching (MPLS) network to provide leased-line emulation services or to carry data streams or protocols that do not meet the format requirements of other multiservice platform interfaces. In addition, these SPAs can be used for low-speed ATM services, including IMA.
The SPAs are the first Cisco router interfaces designed to meet the emerging standards for Circuit Emulation Services over Packet Switched Network (CESoPSN) and Structure-Agnostic Transport over Packet (SAToP) transport. These SPAs do not assume that data has any predefined format or structure. They simply regard the data as an arbitrary bit stream. All data bits are simply transported to a defined destination encapsulated in IP/MPLS packets. Some primary applications (Figure 2) include:
• Transporting 2G and 3G network traffic over packet networks, for mobile operators. Mobile service providers are implementing High-Speed Data Networks (HSxPA) to support new revenue-generating services. The SPA is uniquely positioned for multigenerational migration of mobile networks (2G and 3G), simultaneously carrying TDM and ATM traffic over IP/MPLS networks. This technology provides a mechanism to enable IP/MPLS to the cell site, which can eventually be in place to transport the mobile traffic over IP from end to end.
• T1/E1 circuit emulation for leased-line replacement.
• PBX to PBX connectivity over PSN.
• High-density SS7 backhaul over IP/MPLS.
• Inter-MSC connectivity.
• Preencrypted data for government, defense, or other high-security applications.
• Proprietary synchronous or asynchronous data protocols used in transportation, utilities, and other industries.
• Leased-line emulation service offerings in metropolitan (metro) Ethernet or WAN service provider environments.
Figure 2. Sample Scenario Illustrating Transport of TDM and ATM Traffic Using CESoPSN PWE and ATM PWE over MPLS Network
Service Provider Infrastructures
The SPA can be deployed for ATM service, which provides high-performance interconnectivity, metro, and intra-POP applications between service provider POPs for IP/MPLS transport. It can also be deployed as customer premises equipment (CPE) to provide the data component to the service provider networks.
The ATM service allows service providers to effectively manage the bandwidth at the edges of the network while implementing value-added Layer 3 services. Advanced traffic management features (such as per-VC and per-VP traffic shaping) can also be used to help ensure that traffic from one customer does not affect traffic from another.
With advanced traffic shaping features and support for many ATM service classes, the SPA can be widely deployed in many parts of the service provider network. (See Figure 3.)
Figure 3. Sample Scenario Illustrating Transport ATM Traffic with ATM PWE over MPLS Network
Features at a Glance
• 24 Channelized T1/E1/J1 ports per SPA
• Jitter and wander compliant to ITU G.823/824 traffic interface
• Compliant to IETF draft-ietf-pwe3-cesopsn-07.txt: Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN
• Compliant to IETF RFC 4553: Structure-Agnostic TDM over Packet (SAToP)
• Bit-transparent data transport
• Protocol-independent data transport
• Support for CEoP PWE (CESoPSN and SAToP) transport using Real-Time Transport Protocol (RTP)
• QoS using MPLS EXP
• Configurable payload size
• Synchronous, differential, and adaptive clock recovery schemes, with clock accuracy target of 15ppb
• Configurable egress dejitter buffer up to 320 milliseconds
• Configurable idle pattern
• Support for ATM traffic classes: UBR, UBR+, VBR-nrt, VBR-rt, CBR
• Support for ATM QoS: VC and VP shaping
• Support for ATM IMA
• Support for ATM PWE (VC and VP mode cell relay)
• Support for ATM UNI (3.0, 3.1)
• Online insertion and removal (OIR) supported on Cisco 7600 platforms
• Overall SPA status LEDs
• Per-port status LEDs
Additional Features of the SPA
• Unframed (unstructured) T1/E1 transport
• N x 64 kbps and N x 56 kbps framed T1 transport
• N x 64 kbps framed E1 transport
• Grooming of up to 24 T1 or E1 separate data streams, each able to terminate on a separate network destination
• BITS support
• Configurable clock source for each port
• T1/E1 line diagnostic loopbacks (local line, local payload, and network payload)
Protocol-Independent Data Transport
These SPAs provide completely bit-transparent, bidirectional, point-to-point data transport. Every bit presented to an ingress port is transported unchanged to the corresponding egress port by encapsulating the data bits into an IP packet for transport across an IP network. The data ports do not care about the structure or content of the data stream. Consequently, these SPAs are ideally suited to transport data streams that are not suited to be carried using other platform interfaces. Such data streams might include:
• Leased-line emulation services
• Encrypted data
• Data protocols that cannot easily be migrated to native IP, ATM, Frame Relay, HDLC, and so on
Because these SPAs do not consider the content of any circuit emulation data stream, it is important to engineer the transport network in such a way as to minimize the risk of losing any data packets. To help ensure that a data stream is delivered, without gaps, to the destination CPE, data packets are held in a dejitter buffer at the destination port to eliminate any delay variation (that is, jitter) experienced by successive packets traveling through the network. The dejitter buffer is user configurable up to 320 milliseconds (±160 milliseconds).
Flexibility in Delay vs. Overhead
These SPAs support a wide variety of payload sizes from 1 byte (for very low-speed data streams) to 1312 bytes. This provides the user the ability to control the overall efficiency as well as the end-to-end delay of the system by controlling the packetizing delay.
For circuit emulation services, In order to achieve bit-transparent circuit emulation without bit errors, it is imperative that both endpoints of the circuit use the same bit clock frequency. The network should be synchronized end to end for proper operation. Three options are available for achieving proper clocking and synchronization of network when deploying circuit emulation services over packet network. They are:
• Synchronous mode: In this option, a GPS or BITS clock source is available to be fed into the edge router to clock the packets for transmission. The clock is received from a line interface and is used by the router to transmit the TDM frames, received from the packet network to the final destination.
• Differential clocking mode: Often a GPS or a BITS clock source may not be available for service providers at every possible site, such as a remote cell site. However, they may have a common clock source that is fed into all the elements of the network. In this scenario, the system will use the common clock source as well as observe the timestamps received from the CEoP PWE packets received from the packet network and calculate the differential to recover an accurate clock. This recovered clock reference is then used to transmit the TDM frames.
• 3) Adaptive clocking mode: In some deployments, there is no common clock or a GPS/BITS source available at the remote site. The edge router has to completely rely on the incoming packet stream from the IP/MPLS network to calculate the clocking reference. The clock accuracy, thus derived, should be of very high quality, compliant to the 3GPP mobile standards (accuracy of 15ppb or higher). This is called the adaptive clock recovery mode. The central office will be using a primary clock source reference, and the receiving site will derive the clock based on the incoming CEoP PWE packets.
Unframed vs. Framed Mode
Each T1/E1 port can be independently configured to operate either in unframed or framed mode.
In unframed mode, a T1 or E1 port encapsulates the entire T1 stream (1,544,000 bits/second) or E1 stream (2,048,000 bits/second) for transport across the IP network.
In framed mode, a T1/E1 port supports both unchannelized and channelized operation. In unchannelized operation, a T1 or E1 port encapsulates the entire T1 payload (1,536,000 bits/second) or E1 payload (1,984,000 bits/second) for transport across the IP network. In channelized operation, a T1 or E1 port may be configured with up to N separate data streams (N = 28 for T1 or N = 31 for E1). Each data stream may include any combination of time slots, either contiguous or not. Of course, each time slot may be included in only one data stream.
T1/E1 Clock Sources Supported
On a T1/E1 port, each device must provide the clock used to send data bits to the other device. Depending on the clock configuration of the attached CPE, the T1/E1 port supports any of three clock modes.
If internal clock is specified, the internal oscillator of the router is used to derive the clock used to send data to the attached CPE.
If line clock is specified, the port phase-locks to the clock provided by the CPE and uses that clock to send data to the attached CPE.
If adaptive clock is specified, the spa provides a clock that is locally synthesized, based on the level of data bits in the egress dejitter buffer of one of the data streams terminating on the port, to match the clock used at the source data port.
Some of the highlights of the ATM features supported on the SPA:
• Per-virtual circuit and per-virtual path traffic shaping: Traffic shaping is a function typically provided on ATM edge devices to help ensure that bursty traffic conforms to a predetermined "contract." To implement traffic shaping, the Cisco ATM SPAs support per-virtual circuit and per-virtual path shaping, allowing flexibility and control over every virtual circuit and virtual path configured.
• IP/MPLS-to-ATM QoS mapping: Also supported is IP-to-ATM QoS setting through cell-loss priority (CLP) bit support, which allows customers to divide traffic on different virtual circuits, depending on the desired CoS.
• PWE: MPLS is the primary technology for ATM/IP convergence, and all the Cisco ATM SPAs allow the transport of Layer 2 traffic across an MPLS network. ATM PWE allows a migration path toward the consolidation of IP and ATM networks while protecting existing equipment investment, and it accommodates the scaling of existing services using MPLS. All ATM operation, administration, and maintenance (OAM) functions are transported.
The Cisco SPA/SIP portfolio offers these additional advantages:
– Superior flexibility, providing mix and match of interface types on the same interface processor for consistent services, independent of access technology.
– Pioneering programmable interface processors that provide flexibility for the service diversity required in next-generation networks.
– Innovative design that provides intelligent delivery of services without compromising on performance.
• Increase speed to service revenue:
– The future-proof programmable Cisco architecture extended to 10 gigabits per second dramatically improves customer density, increasing potential revenue per platform.
– Interface breadth (copper, channelized, POS, ATM, and Ethernet) on a modular interface processor allows service providers to more quickly roll out new services, helping ensure all customers large and small receive consistent, secure, and guaranteed services.
– High-density SFP interfaces are featured for high-port-count applications with reach flexibility. Future optical technology improvements can be adopted using existing SPAs.
• Dramatically improve the financials of your routing purchase:
– Improved slot economics and increased density reduce capital expenditures (CapEx).
– The ability to easily add new interfaces as they are needed enables a "pay-as-you-grow" business model while still offering a high-density solution.
– SPAs are shared across multiple platforms and can be easily moved from one to another, providing consistent feature support, accelerated product delivery, and a significant reduction in operating expenses (OpEx) through common sparing as service needs change.
Table 1 shows the hardware specifications for the T1/E1 SPA.
Table 1. Product Specifications
Cisco ASR 1000 Series Routers (CE mode only)
Cisco 7600 Series Routers
Cisco XR 12000 Series Routers
Port density per SPA
24-ports of Channelized T1/E1/J1
24-port T1/E1/J1 cable
Visual status indicators (LEDs):
• SPA status LED
• Per-port LEDs
• Carrier and alarm
• Active and loopback
• IETF RFC 4553 (SAToP PWE)
• IETF draft-ietf-pwe3-cesopsn-07 (CESoPSN PWE)
• IETF RFC 2684 (updated RFC 1483) support for multiple protocol encapsulations over ATM
• IETF RFC 2364 and 2516 for Point-to-Point Protocol (PPP) over ATM
• IETF RFC 1577 support for classical IP and Address Resolution Protocol (ARP) over ATM
• ATM Forum User-Network Interface (UNI) 3.0, 3.1, and 4.0
Features and functions
• MPLS encapsulation for CESoPSN and SAToP PWE transport
• 320 ms jitter buffer
• T1/E1 and nxDS0 CEoP PWEs
• Maximum of 24 T1/ E1 or J1 ports or 191 nxDS0 groups
• Jitter and wander compliant to G.823/G.824 traffic interface
• synchronous, differential or adaptive clock recovery modes
• Targets 15ppb or better adaptive clock recovery accuracy
• BITS support
• Configurable clock source
• UBR and UBR+
• Maximum virtual circuits: 2,000 (subject to overall configuration limitations)
• ATM and IP CoS
• Per-virtual circuit and per-virtual path traffic shaping
• Per-virtual circuit and per-virtual path statistics
These SPAs, when installed in Cisco routers, do not change the power or environmental requirements and standards of the router platform itself. Refer to the platform-specific data sheets for more information.
Cisco 24-Port T1/E1/J1 Circuit Emulation and ATM SPA
Cable for 24-port T1/E1/J1 CE-ATM SPA
Each 24 T1/E1 SPA is equipped with one 100-pin connector. The cable breaks that out to two 50-pin Telco connectors which interface with a patch panel. T1 and E1 lines should be connected through a customer supplied patch panels. Recommended patch panel vendor is Superior Modular Products, part number DCC2484/25T1S.
Service and Support
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Cisco Advanced Services.
For More Information
For more information about the Cisco SPA/SIP portfolio, visit
http://www.cisco.com/go/spa or contact your local Cisco account representative.